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In order to save test device, usually will do Power to Ground then IO to Power/Ground and the last is Io to IO.
6 p" I7 X W* L: g2 _& u0 n( Z8 r: [2 w7 n( J5 j5 I+ ?2 G
The reason is:, r) W r7 j, A( E% X
1. If power to ground can not pass, the rest combination has less chance to pass
2 g+ \% p4 _/ I) r5 A6 F; f" z2. Usually power pin count is less than IO pin count. It is fast to get an idea how the chip's ESD level
/ Z, c2 G+ U: A1 p; U3. If failed, it's easy to find the failed ESD zapping combination |
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