Layout Guidelines for Optimized ESD Protection Diodes

semico_ljj

Layout Guidelines for Optimized ESD Protection Diodes

Karan Bhatia and Elyse Rosenbaum
+ T& ?1 K7 i) aDepartment of Electrical and Computer Engineering • University of Illinois at Urbana-Champaign
1308 W. Main St., Urbana, IL 61801 • Tel. +1-217-244-0578 • Fax +1-217-244-1946 • Email: ksbhatia@uiuc.edu
  |, T' P* e8 y1 O9 H3 {
Abstract - In this work, various layout options for ESD diodes’ PN junction geometry and metal routing are
0 _$ o8 ^) H4 n+ S8 ]6 winvestigated. The current compression point (ICP) is introduced to define the maximum current handling
capability of ESD protection devices. The figures-of-merit ICP/C and RON*C are used to compare the
* Y" c5 u% [/ _8 Z/ sperformance of the structures investigated herein.

semico_ljj

The dual-diode circuit has been found to be a suitable
% D; n3 @2 p1 L* [. ~ESD protection circuit for GHz-frequency CMOS
I/Os [1]. Layout-optimized ESD diodes provide a
1 x3 Y! q; Y( {1 j  ghigh protection level per unit capacitance (C),
2 o5 W+ ]! b1 mminimizing the performance degradation they induce
  \, _! |, q2 ^! f1 x+ {" ton high frequency I/O pins.

mousestack2003

感謝大大分享這些資料∼
* P& v% i+ h8 h! M9 m
! M* f9 m7 W" Z* m. k讓我們了解led的一些事情∼

majorchen

權限不夠,真想看看layout guide要注意什麼...
真是可惜...

guillermo

感謝樓主的分享!小弟最近剛好遇到ESD的問題!

dike

真想看看  與工做相關
小弟最近剛好正在研究ESD中  謝謝

allenearl

发现一个很好的网站,有很多EMC&ESD设计方面的资料,完全免费的.
www.gooemc.cn

hing

很棒的參考資料，謝謝分享！

yoyoseven

謝謝你的分享
/ ~' `! k" c: P9 y: y; l# U9 b現在急需esd的防護方式