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Analog / Mixed Signal Examples, I, x% i! ]9 f2 p3 n5 c- P1 j" x
; J" Z/ _7 q& M9 aBehavioral Models of ADCs
& n2 q, ~" I: r# ^\ams\sampling\; sampling_101;9 g7 Z& C/ I4 E9 }. ~/ V
Sigma-Delta ADC 1st order modulator $ cd \ams\adc\; dspsdadc2; 3 r& h) r3 v. t
Sigma-Delta ADC 2nd order modulator $ cd \ams\adc\; dspsdadc3;
* s+ I; H3 Y( @% w Sigma-Delta ADC 2nd order modulator discrete time (switched capacitor prototype) $ cd \ams\adc\; dspsdadc4;
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Behavioral RF+ H+ Z" F% A1 T
Measurement of Lowpass Filter Freq Response $ cd feed_fwd_2;
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x; f4 \. |, h& I9 @6 k7 u8 nPLLs
+ i" i' ~- B: s! e+ q& {3 k# L; M VCO with phase noise $ cd 5 D. L: e# {( k4 O+ b6 d6 D2 j
Pll with freq domain instruments $ cd \ams\pll;
+ o8 g# [1 I5 v h0 d% z; { g Pll fractional with analog compensation $ cd \ams\pll;
) O8 U4 B. v7 _7 n' P& K1 V+ U Pll fractional with digital compensation $ cd \ams\pll; 9 B$ J% t$ O, @. q
Pll optimization (Nonlinear Control Design) $ cd \ams\pll;
4 l, M) M8 Z- ]1 l1 `+ Q7 m; D! n Carrier and Symbol Timing Recovery (NCO->ADC) $ cd \ams\pll; carrier_timing;
9 P; L$ {8 u% C7 D; P L Carrier and Symbol Timing Recovery (Fractional Delay) $ cd \ams\pll; timing_recovery_1; |
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