標題: free DRAM controller~~~ MIG [打印本頁] 作者: tommywgt 時間: 2007-7-24 12:23 PM 標題: free DRAM controller~~~ MIG Software Support 7 M& b, {- @- ^7 ?; E7 E# Y; {2 B- All MIG designs have been tested with ISE 9.1.01i and Synplicity 8.6.03i. / v/ f9 ^% }( O0 `/ k, Z* W; J" t- k1 d' g9 _: z
Platform Support 9 q1 _' U( n% g9 {! n0 |- f
- Microsoft Windows XP (32 bit) * S' O5 n* ~/ y* E* w& A% r 5 G6 N( }: g4 U0 N3 }3 d0 ~5 BDevice Support 9 Z* A4 `7 P7 H: Q: Z0 Q' E
- All currently available Virtex-5, Virtex-4, Spartan-3, Spartan-3A, and Spartan-3E FPGAs are supported. ' k* P. j2 D b3 H }
: `- W) q7 G0 w7 U" C. WNew Features ) A$ ]/ Y7 T0 a( `! G3 v/ i/ s/ ?2 |General New Features and Changes * @% i+ R) ^6 I# K' a6 A* c# }/ q
- Supports "Create New Memory Part" for all the designs. ; l3 F* n. A2 _
- DDR and DDR2 SDRAM designs for Spartan-3A. ! O! ?. H7 w1 U( [8 O, `3 W4 G- DDR SDRAM is supported for Virtex-5. 8 Y& L0 F; ~( v8 \' W, w
- VHDL is supported for Virtex-5 DDR2 SDRAM and QDR II SRAM. $ b* [: |8 B' j/ E
- MIG now pops up the design notes specific to the generated design. . Q5 ]/ ]( d9 ^1 H- Supports Pin Out compatibility with MIG 1.5 and MIG 1.6 for Spartan-3 and Spartan-3E designs. % p* C T/ l, Y! t- ECC check box changed to Combo box to support Pipelined and Un-pipelined modes. : D4 T% I- n, ?6 T
- Support differential and nondifferential strobes for Spartan-3A DDR2 and Virtex-4 DDR2. " E, D' I# J2 K) c- Pops up an information note if user selects the invalid data width or unsupported data width for a particular FPGA of Spartan-3/-3E/-3A. ; ?1 a, K( J* |( G- Generates a script file for running MIG designs through Project Navigator GUI. This is supported only when the flow vendor is "XST". - f/ E# t: Q7 b# X+ H- Default setting "DCI for Address and Control " is changed to "unChecked". & C' B: b# n; S" R6 h C3 i
- Frequency slider is changed to editable box in the GUI. + q* s% a2 B/ a7 [/ w/ I1 k
- Supports only alphanumeric characters and underscore ('_') for the module name and also for the New Name in Edit Signal Names. , X- F8 R. N r, E# g; L
- Removed console window when running MIG through CORE Generator. : K) r1 g3 C7 N- WASSO table (Set Advanced Options) accepts only numeric characters. + L. B% ?5 l w; U4 ]# }; {& K- The maximum frequency for Spartan-3, -5 is set to 133 MHz if the data width is greater than 32. ( K; F& p. }& D5 _% m, W" M$ e
- Provided web links for all XAPPs in the docs folder of the designs. s9 F* j, x: L) v- Provided link to Data Sheet instead of Log Sheet in the output window. a& {( ~* v+ j( h7 z7 d G
- Support of Constraint "CONFIG PROHIBIT" while reading the ucf in the reserve pins window. , g l: H A& [- WASSO limits the number of pins to be used in a bank per controller. For example in multi controller design, if WASSO is set to 10 in a bank, tool allocates 10 pins for each controller in that bank. ! ~( z! n8 ]4 D J' `& A, H- The designs are independent of the memory part package; hence, the package part of the memory component name is replaced with XX or XXX, where XX or XXX indicates don't care condition. 3 P1 Y1 Q5 d& a& z
+ G2 l- P8 P6 CVirtex-5 New Features and Changes : q) H& q5 v- U
DDR2 SDRAM , Y2 |% L' L$ Z3 Z7 i9 w- New controller with several high-performance features. All the features are described in detail in the Application Notes. , D& t. [% i* g4 u
- Enhanced data calibration algorithms for higher reliability. ; ?. i" R! L; R p: E% |- Bank Management feature is supported. % C% K9 U3 g3 Y' \' r" u' {7 Z( S( B/ ~
- Supports VHDL. ) H: |) s! Z4 ]; p+ x- M0 }
- The user is no longer required to always set address A10 (and skip this bit in their memory space) when issuing a command to the controller in order to prevent an auto-precharge from occurring on the DDR2 bus. The controller now always forces this bit to 0 on the DDR2 bus, and the memory space presented to the user is now linear. 5 I* |1 _# S# g# S
- The User Interface bus has been modified. The command (read/write) is now presented on a separate bus from the address. See the MIG User's Guide for a definition of the User I/F bus. 1 e1 ^# _* |- p4 V' u. X- Several enhancements have been made to the pin allocation algorithms. Due to this, the pin outs will be different between MIG1.7 and previous versions. 9 t$ d9 s5 g7 ]& o% ?) F4 ba. Increased efficiency when DCI is not used. MIG will now allocate VRP and VRN pins for other signals. " e! |# R% [5 A7 H4 K, R, Gb. WASSO is applied to all the memory interface signals. 8 ^. ~) V, Z6 G8 B
c. Signals such as "Error" outputs are not part of the WASSO count. # Q# N3 r' @# ^* }) x- z; b
( t0 I5 @3 S6 kDDR SDRAM ; s6 m0 l% X' `- This is a new design for MIG. Supports Verilog and VHDL. " M3 d3 w5 N6 J$ k4 d a
- Bank Management feature is supported. 2 N$ d' ^" T, Z, ~ H
- The user is no longer required to always set address A10 (and skip this bit in their memory space) when issuing a command to the controller in order to prevent an auto-precharge from occurring on the DDR bus. The controller now always forces this bit to 0 on the DDR bus and the memory space presented to the user is now linear. 2 M7 i- M- Y" w' M7 e& M3 Q3 d) q" B- Y! e
QDRII SRAM 0 T' y, w7 O6 b# [7 Y; N" y, n x
- Added support for VHDL. ' k! Y% s5 _ z0 [6 O: K- Added support for 72-bit designs. : |5 y i) F- H4 P7 y; \ y- Added first level of calibration. This includes a dummy write of 1's and 0's to the memory. This pattern helps to calibrate for the CQ/Q delay. * n3 O( {* U" {* a! I0 F8 f% E- Moved the pattern generation to the phy_write module. This was in the test_data_gen in MIG 1.6 7 @8 E3 }( R. d: ]/ h- A user_qr_valid signal is now being generated to the backend. This signal helps generate the User_qen_n signal to the read data FIFOs. The MIG 1.6 code used the user_qr_empty from all the read data FIFOs. This change was done for timing reasons. $ ]- U$ H! h% O0 S) O: x8 g9 b0 G- Several enhancements have been made to the pin allocation algorithms. Due to this, the pin outs will be different between MIG v1.7 and previous versions. 4 O: q; H+ ^* t" E- L( V5 O
a. Increased efficiency when DCI is not used. MIG will now allocate VRP and VRN pins for other signals. 3 u5 [7 Y, Z3 bb. WASSO is applied to the output signals only. ) |5 M5 G0 M) L+ }: b5 F* Y
+ i) F4 W" f7 U: Q: P
Virtex-4 New Features and Changes 1 f2 x2 ~7 w" s' i: P* a7 NDDR2 SDRAM Direct Clocking * S0 d) e F$ A3 l2 u- Calibration logic now centers and deskews each bit of data. This change improves the frequency performance of the design. d# @% _' ^+ t, a$ K- Independent clock pins are generated for each load in deep designs. This change reduces the load on clock pins. 6 v, O5 L% @" w/ l0 r: J& h; r0 S- There is a new option for the user to select the reset polarity. This option is in the parameter file. The parameter reset_active_low can be changed for active high reset. By default, this is set to 1. ; H; H& S% P% ?
- ECC check box changed to combo box to support Pipelined and Un-pipelined ECC options. 8 A1 w5 [$ a$ s- DQS# Enable, burst type and ODT of 50 ohm are selectable from GUI through Mode registers. $ Z) Y `* M& c- Removed all TIGs in UCF. The reset signal is now registered in every module. " I. s4 V) @% G; `3 L- The IDELAY module now uses CLK0, instead of CLK50. CLK0 is used for the refresh counter. Previously, a divide clock was used for refresh logic. / y4 r9 {0 s& R/ d/ F3 l. F C8 F# W
- SYS_RESET_IN changed to SYS_RESET_IN_N, to follow standard convention for active low signal. 7 a) C! `7 } K4 u6 z( ]! ~- Removed XC_PROPS. The "defparams" that are defined for simulation will now work for both XST and Synplicity. " R% z. r3 k% t& ]3 ]' W- Replaced `defines with localparams for Verilog. - L+ t4 m, D8 Z4 Z6 G
- Read enable in the pattern calibration logic is now generated after comparing two positive edge data and two negative edge data. This removes any spurious read enables. : t$ o- `" b0 w
- Several state machines now use "One-Hot Encoding". % ^5 @. l! M% t- F: a
- Reset generation logic has been modified to make it synchronous with DCM Lock and DCM output clocks. 9 n1 ~: k1 D2 [; C y$ C
- Signal INIT_DONE is brought to top module. ( l! Z( w% n! d8 K$ ?( B+ r
- Removed the UniSim primitive components declaration from VHDL modules. : \3 @6 f) h( M2 u% o) F( @- We now support all multiples of 8-bit data widths even for x16 memory devices. _, d3 D- l+ X+ b5 a- We support memory devices of speed grades -3 and -667. , _- Z3 @! g! A# ` e U# f/ p" Z- Several enhancements have been made to the pin allocation algorithms. Due to this, the pin outs will be different between MIG v1.7 and previous versions. 1 T8 W5 s6 A' z4 a6 X/ B
a. Increased efficiency when DCI is not used. MIG will now allocate VRP and VRN pins for other signals. 7 Q7 }/ F4 O8 H$ D9 `/ |b. WASSO is applied to all the memory interface signals. ( [" G6 [* o3 S
c. Signals such as "Error" outputs are not part of the WASSO count. ! n) n- I2 ~& @3 V- L6 Q% [6 u( e1 Z6 K# ]2 c! N$ p
DDR2 SDRAM SERDES Clocking / u. }; f2 I5 m) K( L! Y* ]' [9 X
- Implemented a new calibration. This new algorithm reduces the DCM utilization and improves the timing analysis. More details are described in the application note. 9 C1 F& I8 _! z8 i3 l
- There is a new option for the user to select the reset polarity. This option is in the parameter file. The parameter reset_active_low can be changed for active high reset. By default, this is set to 1. 6 B: R( t# M6 J$ M1 V% z* h% r- Q- Support for ODT. # n! S# G- ~' M! V% c, C# `
- DQS# Enable is selectable from GUI through Mode registers. $ J9 A3 s% ]2 L
- Removed all TIGs in UCF. The reset signal is now registered in every module. 6 m+ w% c+ r& j0 |% ~- The IDELAY module now uses CLK0, instead of CLK50. CLK0 is used for the refresh counter. Previously, a divide clock was used for refresh logic. & O. @1 c) S. P/ S
- SYS_RESET_IN changed to SYS_RESET_IN_N, to follow standard convention for active low signal. * n" R' ~0 w! }0 f: v+ I' T- Removed XC_PROPS. The "defparams" that are defined for simulation will now work for both XST and Synplicity. 3 ~, \. T3 H* M R- K& r
- Replaced `defines with localparams for Verilog. , y, z; M# `* X+ x6 n. n- Reset generation logic has been modified to make it synchronous with DCM Lock and DCM output clocks. ; v- v; T, y2 P
- Removed the UniSim primitive components declaration from VHDL modules. & p9 H( h* }5 X- We now support all multiples of 8-bit data widths even for x16 memory devices. ' j1 ~7 |+ n1 i& _) @- m- Signal INIT_COMPLETE is brought to top module. 1 }. p0 W! E! B# Q/ F
- Memory devices of speed grades -5E and -40E are now supported. - O1 I4 {1 M0 W% K- C) S; t# O
- Several enhancements have been made to the pin allocation algorithms. Due to this, the pin outs will be different between MIG v1.7 and previous versions. 1 }. p! p+ y0 o) l5 M1 a/ h4 @
a. Increased efficiency when DCI is not used. MIG will now allocate VRP and VRN pins for other signals. 5 \# w7 V3 `5 F0 Q" N0 I4 z! q
b. WASSO is applied to all the memory interface signals. & b# U+ D+ b: b# {' n' X3 m
c. Signals such as "Error" outputs are not part of the WASSO count. 4 s% _0 ]5 B( @" N
- q, D# t M# H; ]" B: o
DDR SDRAM M- n! J, G: f4 g( G* I- There is a new option for the user to select the reset polarity. This option is in the parameter file. The parameter reset_active_low can be changed for active high reset. By default, this is set to 1. $ _' d+ E5 r6 ^; \- Removed all TIGs in UCF. The reset signal is now registered in every module. 0 [( U# o9 B. B3 W" Z
- The IDELAY module now uses CLK0, instead of CLK50. CLK0 is used for the refresh counter. Previously, a divide clock was used for refresh logic. $ r; l! @! K, J0 P* p
- SYS_RESET_IN changed to SYS_RESET_IN_N, to follow standard convention for active low signal. 9 S# i l4 x/ X& Z+ \8 j- A- Removed XC_PROPS. The "defparams" that are defined for simulation will now work for both XST and Synplicity. , u, z, R3 U/ X+ j
- Replaced `defines with localparams for Verilog. % c+ {8 ~! y( `5 N/ D/ y+ y* i
- Read enable in the pattern calibration logic is now generated after comparing two positive edge data and two negative edge data. This removes any spurious read enables. V/ @/ W* E! B4 e; s8 ]" g3 t
- Modified the reset generation logic to make it synchronous with DCM Lock and DCM output clocks. 2 I2 l, K3 d8 T# {3 H, @- Removed the UniSim primitive components declaration from VHDL modules. * S N/ _( n7 b* o9 s. I- We now support all multiples of 8-bit data widths even for x16 memory devices. * F% ^/ Z. P7 m$ \7 w& o' R3 I- The signal "init_done" is now a port in the top module. + {( v ^6 I3 l7 q6 ]
- Several enhancements have been made to the pin allocation algorithms. Due to this, the pin outs will be different between MIG v1.7 and previous versions. % J2 @6 P3 ~- l8 m8 W/ l v' u2 ?# ya. Increased efficiency when DCI is not used. MIG will now allocate VRP and VRN pins for other signals. ' @! w1 D& Y& X! K4 A z
b. WASSO is applied to all the memory interface signals. . F& Q4 A2 Y7 W* Q
c. Signals such as "Error" outputs are not part of the WASSO count. " y1 }! l! |3 m& B% R/ l( [6 K
0 I0 |$ u: M. j! n( b
RLDRAM II 5 U1 R4 g& B6 t9 Y
- There is a new option for the user to select the reset polarity. This option is in the parameter file. The parameter reset_active_low can be changed for active high reset. By default, this is set to 1. ' P _* X. `7 B0 L$ `5 F
- Removed all TIGs in UCF. The reset signal is now registered in every module. & `6 `2 A$ U+ |7 o3 X1 W$ }
- The design now uses CLK0, instead of CLK50 and div16clk. 7 u7 s* A" v9 j/ u" _5 K. }0 a
- CLK200 is changed to differential clocks in mem_interface_top module (Design top). + ?- w2 |+ u5 W' F- I3 o
- The signal sysReset is changed to sysReset_n, to follow standard convention for active low signal. ) p9 B" L6 L+ Q3 g/ c
- Removed unused parameters from the parameter file. ' X+ }/ p3 {6 N8 p
- Removed XC_PROPS. The "defparams" that are defined for simulation will now work for both XST and Synplicity. " ~' A' P& s# H% d y- Replaced `defines with localparams for Verilog. $ ?- z4 c3 o% F# }3 o2 t8 _- Modified the reset generation logic to make it synchronous with DCM Lock and DCM output clocks. 8 H& S8 x7 D" `8 f- v- Removed the UniSim primitive components declaration from VHDL modules. : i0 j. x1 H+ W- The signal "INIT_DONE" is now a port in the top module. 1 i E. P: h1 y6 N7 q
- Test bench: The bank address sequence in backend_rom has been modified so that generation sequence starts with bank 0,1,.....,6,7. The command generation in the testbench is also pipelined for BL = 2,4,8. * K' T- W- l# w4 H' G1 j3 Z
- Replaced "tac" with "Q to data output" instead of "Q to any data output" in the timing spread sheets. w8 u, H [# P1 o3 C- The INITCNT that was hard coded in rld_rst module is parameterized according to frequency by adding a new parameter "INITCNT" in parameter file. : h- O1 K% O, l/ y n7 ]$ ~
- Several enhancements have been made to the pin allocation algorithms. Due to this, the pin outs will be different between MIG v1.7 and previous versions. 3 ~/ |$ s/ x `$ y, w: f
a. Increased efficiency when DCI is not used. MIG will now allocate VRP and VRN pins for other signals. # x1 p2 v4 @% `b. WASSO count is applied on output signals only for SIO memory types. ! R. S7 w; H6 B% `& \ d1 ec. QVLD, which is an input signal, is included in WASSO count for CIO memory types. This is the limitation of the current tool. / D0 E( j: |& C. j; n* W 2 ~0 n. Y& @. o0 i+ ]( c2 wQDRII SRAM # V1 |7 ^! }; O: W) n' _- There is a new option for the user to select the reset polarity. This option is in the parameter file. The parameter reset_active_low can be changed for active high reset. By default, this is set to 1. . q% A. i1 s7 G* \. K" t- Timing for the signal USER_QEN_n has been changed - it is one cycle late. A register for this signal has moved from the controller to the user logic. " L- c' T0 V5 i1 D6 Z/ i
- Supports generation of designs with out DCM. - K! e. s8 n) N1 z- Part CY7C1526AV18-250BZC has been removed from Memory part list and added the CY7C1526V18-250BZC. ; @7 i9 h% N& Q! t
- Removed all TIGs in UCF. The reset signal is now registered in every module. % {6 h C/ b, O( [, K+ b- The IDELAY module now uses CLK0, instead of CLK50. CLK0 is used for the refresh counter. Previously, a divide clock was used for refresh logic. - p1 q' U0 Q, i3 W* }, u7 e- Removed XC_PROPS. The "defparams" that are defined for simulation will now work for both XST and Synplicity. / j! }& }9 D! j9 }+ u0 d- Replaced `defines with localparams for Verilog. + c) F4 D( P0 i9 P
- Modified the reset generation logic to make it synchronous with DCM Lock and DCM output clocks. 5 ^& E/ g; m0 n+ b4 n
- Removed the UniSim primitive components declaration from VHDL modules. 0 U! y+ q0 }! }& |2 `6 n# g- The signal "DLY_CAL_DONE" is now a port in the top module. & x, e1 d. J( J: Q* ]
- The IO Standard generated for system signals are LVCMOS18. Users can change this as applicable. ' B) b0 G7 a% s. r" V: b8 s- Added support for DDR Byte writes. 3 r3 \6 ]1 P/ ]) J
- Several enhancements have been made to the pin allocation algorithms. Due to this, the pin outs will be different between MIG v1.7 and previous versions. * o: D& h8 m6 c6 S' U2 ~& R8 [2 @2 h% Ma. Increased efficiency when DCI is not used. MIG will now allocate VRP and VRN pins for other signals. & a0 k% o8 I7 [% W. ~5 m- Jb. WASSO is applied to the output signals only. : X$ k/ |5 Y# R
c. K/K# clocks, which are outputs, are not included in WASSO count. This is a limitation of the current tool. 8 f1 v, z) R- _; r1 I " C% E6 u# A$ y# ]2 XDDRII SRAM * J- l5 ]1 j$ j- There is a new option for the user to select the reset polarity. This option is in the parameter file. The parameter reset_active_low can be changed for active high reset. By default, this is set to 1. ; U+ i* `) e, Z! [' F" w- Timing for the signal USER_QEN_n has been changed -- it is one cycle late. A register for this signal has moved from the controller to the user logic. ( {% t9 G4 c4 P/ @
- Supports generation of designs with out DCM. # O* e/ T/ c/ p4 j y- Part CY7C1526V18-250BZC has been removed from Memory Parts list. ' ]+ h# {8 M) C' P; @
- Removed all TIGs in UCF. The reset signal is now registered in every module. 6 o8 ?/ C; x2 M/ W- P* i9 J* ^
- The IDELAY module now uses CLK0, instead of CLK50. CLK0 is used for the refresh counter. Previously, a divide clock was used for refresh logic. . m7 H; \4 N! S% T1 U8 v- Removed XC_PROPS. The "defparams" that are defined for simulation will now work for both XST and Synplicity. - g+ ^" E% l. e( H- Replaced `defines with localparams for Verilog. 2 h, M: d# Y. a, E3 J9 G- Modified the reset generation logic to make it synchronous with DCM Lock and DCM output clocks. ) A) A7 A3 i& D. [
- Removed the UniSim primitive components declaration from VHDL modules. / G* c+ [! J( ?
- The signal "DLY_CAL_DONE" is now a port in the top module. ) L& z# L- ^" W. S9 `4 O) C: ]
- The IO Standard generated for system signals are LVCMOS18. Users can change this as applicable. ! @9 t9 I& q: I- j% k0 |
- Added support for DDR Byte writes. * b* X5 ?) T5 l7 q* F- Several enhancements have been made to the pin allocation algorithms. Due to this, the pin outs will be different between MIG v1.7 and previous versions. + q: I* |+ h% W. Q/ fa. Increased efficiency when DCI is not used. MIG will now allocate VRP and VRN pins for other signals. ) m+ N- \7 K2 c- U0 D, T
b. WASSO is applied to all the memory interface signals. . F# v' A; `. |# T# [# x3 e" y0 q6 {c. Signals such as "Error" outputs are included in WASSO count.作者: tommywgt 時間: 2007-7-24 12:28 PM
太長的東東沒人想看吧! / h. u; F7 ~+ p+ {, u( r8 @; F- ?+ f6 z3 R
總而言之, 這是一個由Xilnx提供的free IP, 用來控制memory用的, 目前都拿來接DDR/DDR2 SDRAM比較多! Q) p9 l: y5 S# d: j" B
, n, G3 q* V9 d; s( t
很好用哦作者: steall74220 時間: 2008-5-14 06:08 PM
請問我現在用CORE產生出來的MIG是直接燒在板子上使用嗎??作者: tommywgt 時間: 2008-5-19 12:32 AM
基本上是的. \* N; R- k" X/ X
