Chip123 科技應用創新平台

標題: ASIC設計工程師如何保住飯碗？ [打印本頁]
作者: chip123    時間: 2006-8-8 11:33 AM
標題: ASIC設計工程師如何保住飯碗？
ASIC vs. FPGA？ASIC工程師如何時刻緊跟技術發展的腳步？" B: z! M1 X/ Q' x6 V: T/ l

# \2 j. M! i! N" J& A) nASIC設計工程師如何才能保住飯碗？
) C$ F4 u5 C, C: V! o/ I6 o上網時間 : 2006年08月07日   1 f! y6 D+ g5 m/ Q

1 P6 v/ S5 S. J
當大多數公司依然在使用ASIC設計時，一種新的設計模式正興起──即採用FPGA的設計方法；這種可程式設計方式對硬體沒有過多要求，而且能夠幫助設計業者避免ASIC帶來的成本增加。但是FPGA設計卻在其它方面增加了成本，例如電能消耗。 1 q1 z4 F! @& C. v& ?9 Y# r  Y6 B9 g6 s
; A. Y+ |2 \) {
對於任何一個工程師來說，他們的職業目標都是要決定選擇哪種設計途徑：ASIC還是FPGA？並在選好之後將注意力集中在提高專業技能上。
( B8 n# q6 n# h) h' L" y, N: G  g3 i* j7 X, Z1 Q) r+ a3 x: C
工程設計正成為一門合成性的職業。在我剛入行時，它是一門手藝，一種藝術。現在它已經成為了一門科學，在我們建造更為複雜的系統的時候，這門科學的工具也越來越銳利。工程師必須時刻緊跟技術發展的腳步。
作者: ckl12345    時間: 2006-8-12 02:04 AM
ASIC flow 跟 FPGA flow 太不一樣, 不能混為一談, 以目前來看, fpga 要取代 ASIC 根本不可能, 例如 Mix-mode single chip 如何做就是大問題.! S) K6 _7 n4 `) G5 {$ ]* u& p
作者: sunny.yu    時間: 2008-9-22 08:12 AM
專家觀點：設計工程師提升工作價值的時候到了1 {: i4 C+ l! N& }; i5 K
電子工程專輯, Taiwan - 7 hours ago5 X( z9 m$ |0 Y, S6 q
- z5 Y) l4 d. i8 Y
在這種情況下，許多工程師發現自己的工作職責已經轉變了，需要在設計流程中扮不同的角色，才能跟上價值鏈並維持競爭力。 設計業者正逐漸感受到傳統作業方法的限制所在，也就是硬體和軟體工程師實際上是分開作業；這種模式在如今這個更講究互連以及著重軟體設計的世界已經 ...
作者: ranica    時間: 2011-8-19 02:12 PM
招聘公司：A famous IC company5 F  R% e3 e! ^4 B) {% L7 l
招聘岗位：Asian Technical ASIC leader
; ?; z2 S. \% c0 h工作地点：Shanghai* t: Y5 P! T$ V) `
3 n  e; G, P; U5 F5 R  g
岗位描述：
0 O. M7 W" [* O, u5 z- xResponsibilities - To build designing team in Asia. The number of this team is 30-50 engineers on the 3rd year supporting 100M business in Asia - To provide direct technical customer support and build strong customer relationships - To work with the sales team for our business in Asia - To communicate with different designing team worldwide0 R2 i, W+ x% Y0 l5 \
2 ^+ f+ J2 R  K# v
职位要求：
4 \2 V% @! q9 Q8 R$ D+ FTechnical Qualification (15+ years) 7 U  n8 a: U+ e) M2 h
• Has an excellent grasp of the backend ASIC methodology and flow from RTL to Tapeout in either prior technical contribution roles or technical management or lead roles. This covers o Third-party IP selection and integration o IO ring and package (flipchip, wirebond) co design o Analog IP selection and integration o High speed interface (DDR2/DDR3, Serdes) integration and analysis o Hierarchical physical implementation using a mainstream toolset such as Magma, Synopsys or Cadence o DFT implementation including at speed memory bist and repair and scan compression o IP test considerations such as high speed loop back tests and analog test inmtgeration o Timing closure and sign-off o Tapeout sign-off 1 w& |1 I0 C/ @# A+ I3 ]

) m( k- C/ w% t+ I  c# a  h• Any specialty and experience in ASIC methodology and flow will be highly desirable. Example(s): o Deep expertise with any mainstream ASIC tools or specialized tools along the flow o Low power flow with IPs and implementation techniques o Complex SOC implementation with flipchips and large number of on chip Serdes o Complex mixed signal chip integration with significant amount of on chip analog IPs o Special design and packaging such as MCMs and 3DICs • Ability to contribute in a lead technical or advisory role to key R&D programs in improving or differentiating ASIC flow in power, performance area or cost.
作者: ranica    時間: 2011-8-19 02:12 PM
• Experience with RTL design and verification and product design in any market segment in either technical or management role in a big plus
* i# J/ k, P  O& N( @8 U$ O
  y4 a% L4 L% m$ _• Experience with Tapeout to full product production and rollout including proto bring-up and debug/validation process, characterization, qualification and supply chain management is high desirable. Management and Business Qualification
9 \0 R# \) }& s' X% Y% g+ D
. u# C; }. M1 ]. E5 b$ @( o; N7 W3 V• Direct experience in ASIC technical project management is highly desirable • Has strong leadership qualities that can support eSilicon GM of Asia to setup and grow a local ASIC technical team
1 ~* j$ E" L5 M! G3 y5 y+ S" Q6 |# D. H$ h( M
• Experience in leading and managing global projects and internal engineering or product teams is highly desirable ' @+ O& ^: c% |5 u: ~

' |" s2 T. ]# L8 g( @; j• Experience in interfacing with third-party suppliers within the silicon supply chain (IP suppliers, design service firms, EDA suppliers, backend foundry, assembly and test operations) is a highly desirable
" D4 A5 m" x8 B% _" L+ c  F% I+ |0 a. N
• Experience with key customer interfaces in ASIC support role or other partnering or supporting roles is highly desirable • Well connected in business communities, including at VCs, across the Asian region is highly desirable $ c  `" E; j- `$ H
% w5 j( i# T: {( ]. D
• Awareness of technical developments in the segments which are dominant across Asia so that we can better position ourselves when competing for business is highly desirable * f- K) T+ z0 B. v( @

) r% f" m: [& V3 @• A strong technical leader who will be persuasive in selling our capabilities to high end Asian customers% ?: X: V$ }2 A3 ^% V$ t$ c* R

  m: r+ K& v3 ?0 ?• Has the ability to understand our limitations, but also able to work internally to mitigate the effect of those, so that they do not impede our ability to win business nor allow us to screw-up after winning deals. A strong team player who is flexible, dynamic and capable to partner with other functions as we are growing the Asian business aggressively
) C# |6 d9 ]; g
  g# r' H! s8 q, g• Capable of putting together and giving presentations at high level shows so that we are perceived as a technical leader
作者: ranica    時間: 2011-9-30 11:40 AM
招聘公司：A famous IC company
1 p+ `; E* R0 A$ R: m; f招聘岗位：SOC FPGA engineer
8 V3 z1 v4 b" U8 q* M# o3 D工作地点：Beijing/ W. I, H( R  o9 f) q

9 T4 \( x& h) ]8 H' f- w岗位描述：Job Description:
; Y3 ^2 L3 a, Z& x5 B9 a9 N
- E; e/ E' V2 Q$ |! \ · This position should perform Pre-silicon (FPGA) implementation of the ARM based SoC chips for mobile devices 3 H" X  v: N8 R( t
· Support FPGA user design, testing and troubleshooting · Engage FPGA prototyping domain technical skill improvement and engineering process improvement Responsibilities:
6 W$ b+ \8 v! k5 P# c· Define FPGA prototyping methodology and strategy · Draft FPGA design spec and development plan 2 K; u" o* W& Q% k! i
· Keep tracing and improving FPGA validation technology, methodology, flow and define/improve the engineering processes
' [, `0 ]; W8 K" y) z· Develop FPGA DV and sanity check test case · Implement FPGA integration based on FPGA prototyping strategy 7 D* w% @5 U; W. ~- p3 f
· Experience in Logic design with high-level description language like VHDL/Verilog. It will be an added advantage if the code were written to be FPGA friendly.
作者: ranica    時間: 2011-9-30 11:40 AM
· Understand the custom requirements of a Complex ARM based FPGA design which includes: ARM boot-up requirement, complex clock tree scheme, RAM/ROM inferring, and some basic analog blocks/interface like PLL. Experience with Radio RF will have an added advantage. · Ability to translate ASIC design into FPGA by translating clocks, RAM/ROM and other essential analog block to equivalent FPGA device components and requirements · Familiar with Synthesis with Synplify with clear understanding the interface/timing constraints, and ability to clean all timing issues before P&R phase. · Familiar with FPGA tool to ensure bit file generation fits the size, performance and I/O of the design. · Understand FPGA board requirements and co-design with HW team · Responsibility to verify the netlist so that it will be fully functional when downloaded on FPGA board.
7 y9 ?8 x( ^; u' d( K1 _4 ~1 S8 {& r1 T" `* j
职位要求：; ]0 F# w3 V* r
Requirements: · Candidates must have at least 4-6 years of relevant experience. · Master’s/Bachelor’s Degree in Electrical/Electronic Engineering with an emphasis in IC design · Must be familiar with Xilinx and Altera devices and their tools · Must be familiar with Synplify synthesis tool · Must be able to understand and debug FPGA boards. · Must understand tcl/shell scripts to construct or modify constraints files. · Knowledge about complete life cycle of IC and FPGA development. · Knowledgeable in digital High Speed GHz frequency design and RF Radio is an added advantage · Knowledgeable of ARM based SoC design is an advantage · Good written and communication skills · Experience in WLAN, BlueTooth, GPS, NFC, FM or Modem (LTE, TD-SCDMA, WCDMA) SoC/IP design is preferred. · Experience with muli-site/multi-team/multicultural cooperation is preferred
作者: david_chen    時間: 2011-10-13 09:49 AM
來聽聽大家的經驗談  希望對往後工作有幫助
作者: ranica    時間: 2011-10-25 04:19 PM
招聘公司：A famous IC company
- D* t: {: Y) ]6 E5 N招聘岗位：ASIC Physical Design Engineer
2 @7 x! x5 z' d3 \( ~工作地点：Shanghai+ J6 K( R0 G6 K- s9 q5 ~) ]

/ ]8 e) T* J7 C岗位描述：
7 `) k. y6 z/ n) \- owning, and maintaining P & R scripts for block gate netlist to GDSII - P & R, extraction, Power IR, EM of block level and Physical verification - Work with front end engineer for timing closure activities
' n5 U- p- T* Z% O# C: y$ C  [6 s1 Q! v! [2 A1 F
职位要求：
: f( O  f7 h: L6 X7 a, t$ ?% K• BSEE is required • 3+ years of ASIC/SoC Physical Design; floor planning, power grid customization, P&R, CTS, DRC, LVS, etc... • Experience driving CTS to meet requirements • Experience with either one of P&R tools; Cadence EDI, or Synopsys IC Compiler • Proficiency using TCL, Perl and make scripting
作者: ranica    時間: 2011-10-25 04:20 PM
招聘公司：A Fabless IC design Company
7 s4 y, h; J! V* s招聘岗位：SenDigital IC Design Engineer
+ ^8 N1 r6 Q& Y2 M工作地点：Suzhou
3 [1 c3 b1 b9 ^8 b6 ^2 q: k: L9 G; N( z1 z
岗位描述：
7 j% q4 [) I% w! C职位描述： 1、参与芯片架构设计； 2、负责数字电路的模块和微结构的设计及RTL设计； 3、进行电路仿真，协助芯片的模块级和系统级验证； 4、芯片电路综合、时间收敛、面积优化、功耗分析、形式验证、板上调试等； / j# j2 v; ^. B; Q; m8 l

9 h9 c' ^# J9 s: V* s职位要求：
9 o% {( o& o7 @: q% ?: [& \) s任职要求： 1、通信，信号信息处理，微电子等电子相关专业博士或硕士三年以上工作经验； 2、1-2年CMOS数字逻辑电路设计经验； 3、熟悉数字集成电路前端和后端设计流程，熟悉Verilog等硬件电路设计语言； 4、熟悉数字逻辑电路设计的相应EDA工具 5、有商业芯片流片经验者优先； 6、要求良好的沟通能力和团队合作精神，工作积极主动，踏实好学。
作者: ranica    時間: 2011-11-23 04:58 PM
招聘公司：a start-up company with high performance bletooth and Wifi technology
+ Q/ l! Q0 ~. O* G' ]$ R) w9 m' i招聘岗位：ASIC Design Manager1 X) l0 z8 }' L/ J3 I; g' W
工作地点：Shanghai
: e+ e8 ^' X2 r  m' z0 ]6 i2 X
1 z( g2 d& x* W+ M+ |岗位描述：; y" c  Q+ n9 i4 n" I7 X8 x
Responsibilities: 1. Responsible for architecting each product, and for overseeing architecture definition, block partition, HDL code, synthesis, logic verification, system verification (FPGA), analog IP design, and static timing analysis for pre and post layout. 2. Overseeing floor planning and place & route of the chip, including IP block integration 3. Manage a group of engineers to get the product successfully developed. ; a" S1 K  c3 A* l% N; W

- t' A/ w% `, a- v3 a: E+ D职位要求：
8 M. e. `) E5 x$ iRequirements: 1. 5+ years experience as an ASIC/logic designer. 2. Must understand chip design from architecture down to GDS. 3. Must have good managerial skills. 4. Must be a good team worker, possess a good personality. 5. BS/MS in EE or higher.
作者: ranica    時間: 2011-11-23 04:59 PM
招聘公司：A famous IC company
6 z) [0 ]. `/ K4 k. Z. H  R* W招聘岗位：ASIC - Director of ASIC Engineering" p4 l# g, Z  U! d+ Q, n
工作地点：Shanghai
# g; w/ O6 S2 `$ c4 I$ I# }& L' i+ t- B
岗位描述：
1 ~# F# _+ @+ s! K+ y' c2 g: BJob Description Director of ASIC will lead a team of ASIC engineers and own the development activity of the ASIC portion of one or more ***’s SOC products. The responsibilities include building a world class ASIC team and a state of the art ASIC methodology to enable solid execution of the digital ASIC. The Director will interface with peers in Marketing, Systems, RFIC and Operations to ensure that *** will execute and deliver highly differentiated, low power SOC products that are market winners.
作者: ranica    時間: 2011-11-23 04:59 PM
职位要求：
/ U( F; |' Z1 q* Q% fRequired Skills Experience and Skills: A motivated self-starter, team builder and an inspiring and effective leader. Strong communication skills and ability to interface with multiple teams such as Marketing, Systems, RF/MS IC Design and Operations. Experience in communication chips (PHY and SoC) developments. Prior experiences in commercial digital ASIC development from specification, design, tape- out to characterization and production. Strong organizational skill to help with project management of complex SOCs. Drive ASIC methodology and IP and tool evaluation. Technical expertise on the entire ASIC design flow—architecture, logic design, RTL coding, verification, FPGA validation, synthesis, DFT, timing closure and physical backend leading to tape-out. Experience with low power techniques is a plus. Required Experience Education/Training: MSEE required (Ph.D. preferred), 10+ year industrial experience. 5+ years’ experience in managing ASIC teams and leading product development.
作者: amatom    時間: 2011-12-19 11:32 AM
Altera的抖動和SERDES架構專家當選IEEE會士
8 W/ i+ }( j1 A4 Q1 X7 \' a. N5 t6 F6 B李鵬博士（Dr. Mike Peng Li）在抖動測試技術設計上的貢獻獲得肯定
* {: H$ G. G$ A3 W6 H1 \- _. W[attach]15049[/attach]
9 ?3 C! ^4 c% g& N0 o) `/ e/ G0 j+ x6 B: t( W6 M0 c; z
2011年12月16日，台灣——Altera公司（Nasdaq：ALTR）今日宣佈國際電機電子工程師學會（IEEE）遴選李鵬博士（Dr. Mike Peng Li）為IEEE會士。李博士在Altera負責架構與工程的研究與開發，他在抖動測試技術設計上的貢獻獲得肯定。
! q+ E$ f% X* ~7 m% y( r* _' x/ j/ V: H% e  c2 j
李鵬博士的成就在於具體化與推進產業在現代光電元件與系統的抖動基礎科學的理解，這些技術可用於抖動的驗證與測試，以確保效能與可靠性。基於他在半導體產業的貢獻，IEEE遴選李博士成為其最高層級會員。
作者: amatom    時間: 2011-12-19 11:32 AM
Altera全球營運與工程資深副總裁Bill Hata表示：「Altera培育出一種創新文化，讓我們能夠解決一些在Gigahertz與Terahertz時代所出現的最複雜工程挑戰。今日的高速、先進設備，都需要我們創造新的技術，以解決獨特的問題。李鵬博士在抖動、高速鏈路和SERDES架構領域的專業知識，讓Altera能夠推動我們產品與技術的發展，他當選為IEEE會士實在當之無愧。」& W) G% H+ J+ K* f% l

7 w- }2 m0 D5 u: W. ~0 `李鵬博士一直推動高速的 I/O（HSIO）與抖動量化與測試技術的進步，突顯出數個到幾十GHz/Gbps的訊號／抖動測試／分析系統的技術發展。他一直是發展現代抖動理論與相關的模型建立和測試方法的先驅。李博士曾撰寫兩本書，有超過50多個出版品，20個已獲得與正在申請中的專利，是HSIO和抖動標準文件的主要貢獻者。這些作品都支持了快速HSIO的技術進步，為一些在測試、模型建立與抖動分析、雜訊等，並在開發需要全面性、準確的理論、模型、演算法的高速訊號與高效能的硬體與系統時，為所遇見最具挑戰性的問題，提供解決方案。/ \# K/ w( X9 O. ~' d

1 z# e+ {1 q# L$ g關於IEEE與IEEE會士等級
! K. e: H2 P) ]/ SIEEE的會士等級，是IEEE董事會在依據某人在任何IEEE相關領域擁有傑出成就時所頒發，在任何一年所選擇的會士總數不能超過總投票成員的千分之一。IEEE會士是等級最高的成員，是科技社群所公認的殊榮，是一個重要的職業生涯成就。在2012年有329個人已經提升為IEEE會士。IEEE是引領世界為人類發展先進技術的專業協會，透過其在160個國家的385,000位成員，該協會是一個從航太系統、電腦與電信到生物醫學工程、電力和消費性電子等種類繁多領域的領導權威，如果您想了解IEEE或IEEE會士計劃的更多訊息，請瀏覽www.ieee.org。
作者: globe0968    時間: 2012-1-19 12:15 PM
標題: 全球產業領導者Jeff Waters加入Altera 擔任資深副總裁與總經理的職務
2012年1月19日，台灣—Altera公司（NASDAQ：ALTR）今天宣佈在產品開發、市場行銷與全球市場區域管理擁有20年經驗的商業領導者Jeff Waters將加入Altera公司，擔任軍事、工業與電腦運算部門的資深副總裁與總經理職務，Waters與他的團隊將負責這些領域的系統解決方案開發與市場行銷工作。他負責向Altera的總裁、執行長與董事會主席John Daane報告。
6 h. ?  ]9 [, R' {6 H# M5 O& x. K$ L- @
Daane表示，「Jeff在管理產品線與市場行銷組織、維繫客戶與發展全球團隊方面，擁有經過驗證的卓越成績，是Altera的理想選擇，我們非常高興擁有Jeff在我們的管理團隊中，能夠為我們的事業發展爭取更多複雜的矽智財模組與系統解決方案，以滿足客戶的需求。」
5 T0 g' J4 [; G% K% K' Q0 w. x2 w6 j
Waters先前曾在美國國家半導體公司的日本分公司擔任了三年的區域副總裁職務，負責領導業務、市場行銷與營運工作，隨後返回美國，擔任德州儀器／美國國家半導體公司的精密訊號路徑部門副總裁職務。此外， 他也擔任研發與管理顧問工作，管理類比與單晶片系統（SOC）產品集團。他擁有聖母大學（University of Notre Dame）電子工程理學士的學位，以及聖塔克拉拉大學（Santa Clara University）電子工程碩士與西北大學（Northwestern University）凱洛格管理學院（Kellogg Graduate School of Management）的工商管理碩士（MBA）學位。. r! a* k- q. N. ^0 Y5 }
& {! A! K: |, Y2 b
Waters表示，「我很高興能夠加入Altera團隊，公司的文化、技術卓越與專注在客戶創新上的表現，提供一流的成長基礎，我非常期待能領導我們的團隊進入下一段令人興奮的公司成長階段。」
作者: ranica    時間: 2012-5-7 03:19 PM
招聘公司：A famous IC company9 H" ~" G; w$ g$ b# U# U+ t
招聘岗位：(Senior) ASIC Design Engineer
& m) Y5 s) Y" m7 |' N3 |工作地点：Shanghai
$ F# |* ~7 }* Q9 h- W6 k* e1 d$ I9 \, e( C, F' D. ~* u* X- x
岗位描述：
$ c* x- e4 |1 n& }1 l1 XASIC front-end engineers will be responsible for design and development of ASIC functional blocks in communications SoC products. These include building blocks for communications/DSP functions and/or System-on-the-Chip (SoC) blocks (such as CPU subsystems, I/O peripherals, and memory controllers… etc.). & O, r3 V1 O: M2 q
7 I% K( g* n0 I' Q
职位要求：
9 m; y0 a# d9 _+ B1. Good understanding of the whole ASIC design flow, from Micro-architecture design to silicon bring up. 2. Good understanding of modem verification methodology 3. Strong logic design/debug ability and good RTL implementation skill. 4. Ability of block/chip level synthesis and equivalence check. Can work closely with backend for physical implementation 5. Ability of C/C++ programming. Familiar with at least one script language. 6. Strong communications skills. Must be able to communicate fluently in English Following knowledge and experience are also strongly desired: 1. Good background in communication/DSP theory; 2. Knowledge in embedded MCUs and AMBA protocol; 3. Experience of working with oversea teams. Required Education and Experience • Sr. Design Engineer: BSEE required, MSEE preferred. 5+ years of hand-on design experience. • Staff Engineer: BSEE required, MSEE preferred. 8+ years of hand-on design experience.
作者: sophiew    時間: 2012-6-7 05:34 PM
標題: Altera任命業界資深人士Scott Bibaud為資深副總裁兼總經理
2012年6月7日，台灣——Altera公司（NASDAQ：ALTR）今天宣佈，從事通訊行業長達18年的資深人士Scott Bibaud加入Altera公司，成為通訊和廣播業務部的資深副總裁兼總經理。在這一個領導職位上，Bibaud主要負責監管全球通訊和廣播行業系統解決方案開發和市場。他直接向Altera總裁、執行長兼董事會主席John Daane匯報。
  [( h( d. F' G# m$ Z; h4 L' K* }& n* Q1 G) ]( R8 f# w" c+ i
Daane表示：「Scott曾在世界上最大的行動通訊公司有過豐富的工作經驗，開發強大的客戶合作關係，這都令人印象非常深刻。他在ASSP和ASIC產品開發上的深厚背景以及在營運、財務和跨職能方面的領導能力，令他非常適合Altera的管理團隊。」
+ a! A' D  L. d. P3 r: N2 F" U
5 p0 h# F; l# H8 D/ RBibaud最近的職位是Broadcom公司的執行副總裁兼總經理，負責公司的行動平臺團隊。在此之前，他領導的團隊負責Bluetooth®業務線，推動了Broadcom公司的收益增長，讓公司業務擴展到了很多新的市場領域。他還曾在Conexant公司擔任過領導職位，負責管理諮詢。他獲得哈佛大學企管學院的MBA，以及倫斯勒（Rensselaer）理工學院的電子工程科學學士學位。
/ O: m! E9 O' P/ g9 q( o3 A2 L) `
Bibaud表示：「與Altera團隊一起工作，有很好的機會充分發揮可編程設計邏輯的優勢，在通訊領域實現客戶成功。通訊是非常活躍的領域，充滿創新，是當今行動社會的核心。Altera在客戶成功方面有著非常出眾的記錄，定位在為支援下一代系統提供最新的解決方案。」
作者: mister_liu    時間: 2012-6-29 05:17 PM
標題: 日立採用明導國際Olympus-SoC佈局與繞線平台開發重要ASIC晶片
2012-06-06-明導國際今天宣佈，日立公司(Hitachi, Ltd.)已採用Olympus-SoC™ 佈局與繞線系統開發大型ASIC晶片，並已成功達成40奈米、9000萬邏輯閘設計的投片。6 z6 q9 j& ~5 C2 o) R- n

; y6 T# l3 M3 w6 B日立公司資訊與電信系統部門MONOZUKURI創新中心的資深總監Kazuhisa Miyamoto表示，「日立透過採用Olympus-SoC的大型展平(flat)模式功能，輕鬆達成了9000萬個邏輯閘設計的時序收斂。Olympus不僅能夠更容易、更快速達成設計收斂，還能得到更好的結果品質。明導國際與我們的研發部門保持密切溝通，每當我們遭遇困難時，都能迅速提供支援。能以Olympus-SoC成功完成投片，對我們的業務發展來說深具意義。」
# f) T0 i! h' I+ M1 e1 {9 r # l+ X6 `7 l( A7 k2 V
Olympus-SoC佈局與繞線平台的獨特、專利架構是專為解決大型、複雜IC設計問題所開發。Olympus-SoC擁有非常精簡的資料庫，能以展平模式處理具備數千萬個邏輯閘的全晶片設計。再結合原生多角多模最佳化技術，能改善大型晶片和多模多角情況的時序和訊號完整性。此系統亦提供多電壓、低功率設計的完整支援，包括時脈樹最佳化和漏電流降低的先進演算法。Olympus-SoC繞線器也可用來處理先進製程節點的複雜設計規則檢查(DRC)和可製造性設計(DFM)需求，包括樣式比對和以優先級為基礎的(priority-based)建議規則支援。Olympus-SoC系統可與Calibre®驗證和可製造性設計(DFM)平台緊密整合，能以簽核驗證 解決設計階段的製造變異性。" y3 r% b3 B1 o4 l2 a! z0 {0 w

3 `4 F! b' V; j  n  n: V: ?- ~明導國際佈局與繞線部門總經理Pravin Madhani表示，「許多以舊式架構為基礎的佈局和繞線工具，到40奈米和28奈米節點就已不敷使用，因為它們無法協助設計人員克服千萬個邏輯閘設計的複雜度，以及高效能與低功率挑戰。Olympus-SoC架構是專為因應更小幾何節點的容量、效能和低功率需求所建置。Olympus-SoC還能與Calibre緊密結合，讓設計人員建立可滿足晶圓廠所有簽核需求的“第一次就正確”設計，不再需要耗費高成本進行重覆設計。」
作者: ritaliu0604    時間: 2013-4-24 01:55 PM
標題: Senior ASIC engineer
客户 a start up company with innovative technology# L* f& j% q2 l6 l1 `3 O
地点 Shanghai
/ f/ F& N& o' u% V' W
( I$ l) V/ \; C( m" x职位要求& G* [$ H& \+ Y  d! D% j0 ]+ w
5 + years experience in ASIC design -> must
6 S  z4 P5 a* o+ D( q/ g3 j· MS in Electrical Engineering (or equivalent) is a must have% @2 Z8 T" o+ l/ B# Z# `
· Experience with WIFI baseband/MAC or related wireless baseband technology desired -> plus
2 ^  ?$ t" x$ [. d  k2 [, c5 Z1 u· System on Chip (SOC) Integration Experience, including AHB/AXI, CPU integration -> plus8 \- Z- u  n+ h3 y2 V# z
· Experience with interfaces such as SPI, SDIO, USB -> plus
1 q! v6 X1 v$ N0 Z; H· Working knowledge of networking protocols such as TCP/IP, 802.3, 802.11 -> plus
/ D! X  Q! v9 J! q6 \. [· Must be expert in Verilog RTL language -> must* I7 }8 W( j* X  P7 C( f, u
· Must be familiar with the ASIC design flow from RTL through synthesis, including the tool flow. -> must
0 ?+ e+ e; k; O! y0 z: r· Verification experience – Verilog, System-Verilog, Coverage Analysis -> must for verification engineer, plus for design engineer
7 S2 G1 N' L& o. b; m! R6 j6 U· FPGA emulation experience -> plus6 {+ x( G8 w6 g- R
· Chip bring-up experience, including use of Logic Analyzer and Oscilloscope for debugging -> plus
( j% u3 v  t5 [; F6 W$ L* W· Experience with digital backend
作者: ranica    時間: 2013-5-15 03:42 PM
Senior ASIC engineer
5 y! Y* G- _" D. ^2 J& \+ L客户 a start up company with innovative technology
# |/ ]5 [4 G( P* B# i$ s地点 Shanghai" y$ S- M# g  W9 l5 X

6 k2 d) Z) Z9 h% `( k职位要求
5 f1 }! l! }/ V  }* m, H/ ~5 e5 + years experience in ASIC design -> must " D* L% t6 C3 g  H
· MS in Electrical Engineering (or equivalent) is a must have
! J1 H' O: }5 Q9 x; ^7 t* j3 D· Experience with WIFI baseband/MAC or related wireless baseband technology desired -> plus
- o' @4 T' P$ `) v8 z4 i· System on Chip (SOC) Integration Experience, including AHB/AXI, CPU integration -> plus
" Y1 P9 U/ H# E) `2 ]: Q· Experience with interfaces such as SPI, SDIO, USB -> plus; k; O/ J6 X$ b" p4 p
· Working knowledge of networking protocols such as TCP/IP, 802.3, 802.11 -> plus( Y: h6 E" h" H" S
· Must be expert in Verilog RTL language -> must* v! L( t% t$ c7 w9 `: a5 g5 y. w
· Must be familiar with the ASIC design flow from RTL through synthesis, including the tool flow. -> must
, v+ ~# z" F/ c9 U9 _( U, p1 i* a" ~· Verification experience – Verilog, System-Verilog, Coverage Analysis -> must for verification engineer, plus for design engineer
2 f$ k) A9 w+ T6 r6 b· FPGA emulation experience -> plus
. u% d* Z- @: j6 k. E· Chip bring-up experience, including use of Logic Analyzer and Oscilloscope for debugging -> plus' B- t. m. q- l% j. H% e& T
· Experience with digital backend
作者: ranica    時間: 2013-5-15 03:43 PM
资深数字设计工程师& v1 o, I" W3 W* y
客户 A start6 o8 a9 @; H( r
地点 Shanghai
0 c! q7 Q3 q6 H  X' s$ X: d
  z; Y0 y& \/ _6 j# h5 X职责:2 s' Z4 Z- R5 L0 x, ?  H
参与从产品定义到量产的整个流程。0 _5 \+ g* |7 h. M+ z9 P8 T
参与芯片架构定义。
5 E3 {" ~) ?( |  U; Y; {5 EASIC设计，RTL编程和RTL仿真。
+ ]6 q* \$ S: A( k. D综合和FPGA评估。
9 Y" H: M" |, _1 \) [6 A# V" X与应用测试工程师合作，提出最优解决方案。
8 P8 H# u. E& |% b0 V/ P- ]
6 C5 t0 k: ]0 ^/ W: q& g6 S职位要求：8 _( O: i" ~8 L2 D* p2 Z- Y/ q0 p
电子工程相关专业硕士毕业。% T, }5 L/ }+ O) Y$ @
3年至5年以上RTL设计经验。
" v0 T4 y; b8 e: ^6 i* L有音视频领域经验优先。/ C% _9 ~& w: }. M5 |$ k
良好团队精神，学习能力强，敢于接受挑战。
( M+ f: z# h' T( m2 j4 |必须具备RTL编程、仿真经验。) D( ?  i( C- B
熟悉FPGA验证优先。
作者: ranica    時間: 2013-5-24 01:40 PM
资深数字设计工程师- D: S- v) a& f. n/ P7 r2 [6 P
2 M% @4 e: l: w: |) i+ D
公      司：NO.233-A start-up company1 S  ]& e( H  o7 m* ^
工作地点：上海
" l: H9 k, L2 K8 {0 ]
4 j9 H7 o) `7 Y6 {5 `8 R职责:
, }0 m. N7 ?8 O' s- K( r8 \参与从产品定义到量产的整个流程。, \; k( ?+ e' _# w/ W$ e/ x
参与芯片架构定义。/ t; I$ J. b  X2 ^  U6 z
ASIC设计，RTL编程和RTL仿真。
& B8 S+ d. Z& |  [$ k- @5 y+ Q综合和FPGA评估。! j$ `7 [% c6 |. B/ G. [
与应用测试工程师合作，提出最优解决方案。
8 t5 q# {/ U/ t# M2 \, t. Q9 V7 g0 b4 w' b- g
要求：2 u6 X( G; M9 T- j3 d4 b: q8 I
电子工程相关专业硕士毕业。6 \! @6 N9 a' G. N4 l0 \/ G
3年至5年以上RTL设计经验。' Q( v0 e8 _/ L5 n8 K/ _3 x9 s) t, w
有音视频领域经验优先。$ ~7 u( r, S% W& H4 b: }) ]
良好团队精神，学习能力强，敢于接受挑战。# s+ u6 ?$ b" X
必须具备RTL编程、仿真经验。
3 N# z* |; I- d2 ?熟悉FPGA验证优先。
作者: tk02561    時間: 2013-6-17 05:40 PM
安森美半導體與空中巴士完成合作開發用於A350 XWB 飛行控制電腦的複雜ASIC
/ p8 g) n1 O2 w, m% p5 S安森美半導體的110 nm製程技術平台達致開發關鍵航空應用的高度可靠方案/ Y3 A0 F+ c, ]2 ~0 z* w
/ x6 ]) z. [& Y& X
2013年6月17日 – 推動高能效創新的安森美半導體(ON Semiconductor，美國納斯達克上市代號：ONNN)與領先的飛機製造商空中巴士(簡稱“空巴”)完成合作開發及投入生產一款複雜的專用整合電路(ASIC)，應用於空巴A350 XWB寬體飛機的飛行控制電腦。這定制硅方案的代號為JEKYLL，使用了安森美半導體內部的110奈米(nm)製程技術，在安森美半導體美國奧勒岡州的Gresham工廠製造。JEKYLL項目的完成，反映了雙方從可行性評估到第一次即對原型到按期為A350 XWB量產的成功合作。& y0 `0 z' b7 z! V# f* `9 [0 S3 g) \

9 J+ Z, k* w/ C" {' C. ?  V此ASIC的設計符合D0-254航空要求，並滿足空巴嚴格的可靠性及產品長壽的需求，為空巴A350 XWB飛機的飛行控制主電腦提供優化的性能。安森美半導體被選中參與這個項目的原因有多種，包括公司在複雜ASIC開發方面的專業知識和技術、著力於軍事及航空應用、一流的品質水準、毫無疑問的長期產品支援，以及對D0-254要求的深入瞭解。
7 \* I: d9 D) O- s6 K9 M3 j/ U2 c0 G
安森美半導體軍事/航空、數字、晶圓製造、整合式被動元件(IPD)及成像感測器產品分部副總裁Vince Hopkin說：「能成功開發這複雜的ASIC是空巴與安森美半導體通力及詳細的合作成果，彰顯我們致力於服務講究高可靠性的航空市場。我們公司內部的110 nm技術極適合於此要求高性能的應用，是我們從40 nm到0.35 µm之強固技術方案組合的一部分。」
; P! l. a9 o: P
( Q7 M% O9 s% m2 x* `, v) w9 x歡迎蒞臨安森美半導體於2013年6月17日至23日在2013巴黎航展的展台(2B館H58展位)。更多有關此航展的訊息，請參考：http://www.paris-air-show.com/。
作者: ranica    時間: 2013-7-2 10:04 AM
Staff Digital Design Engineer! e$ H1 X/ l! l/ D* u  v0 L
公      司：NO.82-A famous IC company/ q) L1 y$ J& ~, f- D: B; `1 b
工作地点：上海
: [7 i7 ?6 v. J( ~
- C* A. H( \+ T( t2 a0 Y7 ?+ ^: ?职位描述! z% W, v$ k. ~' u6 ~6 n
A worldwide leader in the design and manufacture of microcontrollers, capacitive touch solutions, advanced logic, mixed-signal, nonvolatile memory and radio frequency (RF) components. Leveraging one of the industry''s broadest intellectual property (IP) technology portfolios, be able to provide the electronics industry with complete system solutions focused on industrial, consumer, security, communications, computing and automotive markets. As a global company with 5,100 employees worldwide, she operates in more than 40 countries and has 30 design centers, including locations in Shanghai and Taipei. Her solutions enable their customers to lead the markets they serve by creating products that are more powerful, smarter, energy efficient, lower cost, and more versatile than ever before.
% r9 `; P9 D8 }/ j- i- s: n. o
/ U$ z2 J! D8 AResponsibilities
& r+ |) u( ~) G8 N: z• Develop ARM-based MCU/SOC products
8 y/ _% d' T# Q6 n+ g3 d0 T职位要求3 ?% k: `4 ^9 L0 V
Mandatory Skills - H7 S+ c& D7 {' T+ a6 q
        Very good Verilog coding and simulation capability.
, o" x5 W  X6 h& k$ p! q  ^* n) S Familiar with ASIC design flow, including related tool experience and skill, such as DC , conformal , formality , Tmax or PT.
7 Z) Y$ }; a$ H9 G6 {        Fluency in English and good in communication skill. : d4 n2 ^  c+ x- H+ ~$ `+ R/ I
Preferred Skills
5 H3 p% @6 B( b0 D        ARM-Based MCU or DSP related experience and knowledge is highly preferred. ) X0 h* c% \+ B1 E# j9 b
        Understanding of embedded firmware and programming is a plus. % d0 }9 x2 H' J6 |9 t  \
        Unix/Linux shell/script programming.
( ^% Q- T4 [; _1 LEducation ; o' s+ x4 q- u
Master Degree of EE or related. ! w0 {( }9 ?& j5 Z& L4 q5 b
Experience , _( G0 [; S# y9 N' K% I2 k; g/ G. e; g
        8+ years of design experience. # }+ g! ?# a$ o/ O
        At least two years of US or Europe-based company experience. 9 s1 _4 S5 o: X7 X7 O6 Z! q
Position: Regular 2 O# f1 B7 I$ t$ Q6 e
Shiftay 1 `! k9 j; h) k$ g! L( |6 \5 W4 g  h( l
Location: China
作者: ranica    時間: 2013-7-5 10:03 AM
ASIC Design Manager
5 A* }; A5 {" S2 o$ X公      司：a provider of highly integrated semiconductor company" g1 s7 L. ~! i. y  S% Y: T
工作地点：北京
$ U* p3 ~* _& M
: N% d  u& E$ `# o1 N8 t# vDescription:  . g  {& A0 a- ^( F* G
Roles & Responsibilities:
( V9 c/ i# Q0 n1 Y* |# b. G4 V+ K* JIn charge of logic design from spec to tape out and bring up  
, T* f  X$ n. B" E3 ]8 zMicro architecture and implementation  6 u9 ^7 M; S. Z
Working on or lead logic design, simulation, validation  
6 b! v8 s& R0 @( ~& P4 {Coordinate analog design, bring up and thouble shooting
8 f7 a' k# n1 v7 }3 F8 h( P3 x3 E& y
Requirements: ( S+ z& X8 R4 h! a. s
5+ experience on IC design  
, m0 b* j5 x2 k7 Y/ F& y4 kDeep knowledge and skill on ASIC design flow including RTL coding, simulation,  synthesis, timing closure, power estimation, formal validation ! N* p, D0 e1 ^
Deep knowledge on digital baseband or SoC design   
* H. r* S5 R) N. j; S8 T7 ?Master degree or higher.  2 m  X- v9 l/ y6 E6 D/ T
It will be plus having experience to lead and deliver ASIC project
作者: ranica    時間: 2013-7-23 02:16 PM
数字工程师
* K# ]8 `5 j( Z7 W: v
& k7 j6 {$ b( _公      司：IC设计公司2 x. _( C2 \6 S6 M" O- Z; G9 s
工作地点：深圳
5 l" J% `, k& a; w8 o  Q) p3 t* t& i& n
职位要求
( r* x- ~. J# K/ k2 {$ e0 ]1、 熟悉数字电路设计流程方法及工具；
+ I) p* y) S1 d, D$ m2 g( {2、 精通LCD数字电路设计；
" d/ J, D9 A* I9 S3 o" F& C4 \3、 具有两年以上MIPI设计经验。
作者: ritaliu0604    時間: 2013-10-16 02:21 PM
资深变频空调方案研发工程师
- ]. e, g( E' W6 ^8 T  I0 W
6 v1 ^" C% o( v6 s4 b/ [2 ~8 r  S公      司：A famous IC design company in shanghai, J3 A. k0 c3 G" q- X
工作地点：上海/ M1 ?/ z2 p0 C( ?$ P% K/ }/ {1 R
5 ]* B4 U% Q: S
职位描述5 h. b7 G0 Y9 |' j
從事變頻空調控制軟件的研發。 ' r9 v( J) B$ J& k0 s+ B

" l% @' U" ~; w! O9 p职位要求/ F- j) \; S" A& n% ]) _6 R4 Z1 b
有變頻空調控制軟件的研發經驗，熟悉變頻空調控制算法及相關技術
作者: ranica    時間: 2013-10-30 02:15 PM
ASIC Design Engineer
) o+ \) \. p. i* H4 }! q# X  C' _( b% g
公      司：A famous IC company7 n/ ]0 I$ T- _5 x
工作地点：上海- D8 Q! ]; ~) B% U2 q: ~, r
. d, ?) s4 E" m1 p5 z
The Role:
; z$ q! q% A: S  L, ~# Z0 Y& N; [, \·         ASIC design  # m7 @5 y* Q8 n, Z% N" H
·         Work closely with the California teams * o/ r3 _" o% t5 I, H# |
·         Support chip tape out and bring up
8 @* a2 V( l  ~3 K% F8 }) y# Y0 y" H2 g$ R) A! I; v8 Q) b
Requirements: * n' m. u! ^; G
·         3+ years experience in ASIC design * P  B" Y* Y" Z, Y# I7 x. W$ Y
·         BS in Electrical Engineering (or equivalent) is a must have, MSEE is desired
, i* k( H) C+ J& r/ v$ t% f·         System on Chip (SOC) Integration Experience, including AHB/AXI, CPU, Interface integration * u* i- }, I$ [7 q
·         Experience with WIFI or related wireless technology (i.e. WIMAX, 3G, LTE, etc.) is a plus / E4 N+ O% S0 u$ U% S
·         Experience with interfaces such as PCIe, Ethernet, DDR, USB ) v( L& w$ z8 p+ P7 {4 e8 ^
·         Working knowledge of networking protocols such as TCP/IP, 802.3, 802.11
9 o; a# B- ]0 [1 p1 {. P/ v4 [/ l& j·         Working knowledge of C programming language 5 u7 n) z! u1 D' ~' L" l
·         Experience with Medium Access protocols a plus
' \. T5 g. P  j' b0 j3 H8 L% g·         Must be expert in Verilog RTL language
( k+ l. D8 t: c1 l! [( S% _- j# Q·         Must be familiar with the ASIC design flow from RTL through synthesis, including the tool flow. . C9 e- I& b7 v3 b7 h2 B' b
·         Verification experience – Verilog, System-Verilog, Coverage Analysis
! {) v2 K# h6 e1 @9 Z3 g& u·         FPGA emulation experience ( F/ g, U. v. y& F
·         Chip bring-up experience, including use of Logic Analyzer and Oscilloscope for debugging
作者: ranica    時間: 2013-10-31 01:53 PM
IC PM
- P* J) L( w" ]; ]: S
! h* f/ f  c3 f. W- G: E9 G公      司：A famous European IC company
9 ~1 a. F8 |( Q! M& h' l4 l工作地点：上海
5 O# e6 T9 ~! y  b" H$ D% M  t1 \. o# O/ P  e9 P2 d
Roles and Responsibilities   7 @- \% ^+ B0 X& A, ]: g% A
1. Manage ASIC design project according to product development process   
; r$ Q+ v. g; r) Z- S* }     - Coordinate the different resources to deliver the ASIC product in time and with good quality  
5 h" C# r$ ]* s7 N/ Y4 }( B! r     - Responsible for the communication of the whole project team  4 v+ Y/ Y7 @8 u6 V
     - Participates and drives internal review of each development phase and make proper justification  9 |, r5 l, G: U- V  b
     - Develop and manage project schedule, resource, communication and critical path  
# E1 V! n' s; \9 s/ p* S+ l     - Identify risk and develop mitigation plan with the project team  
) `! j- }, H1 |5 {8 h2. Closely work with IC manufacturing and testing / qualification to drive the ASIC products into mass production in time and with good quality 6 T! Q. v' A$ T  L
3. Work with the financing and control the project budget" l* B5 G6 C& R; Z% b& W8 j

9 U' K' V) v5 k$ U3 G  n- Y! uQualification Requirement   # \8 o- b2 X* s0 H( ?# Y( `
- Master degree or above in Device Physics, Electrical/Electronics Engineering or equivalent  
$ [% O' V1 [" R7 ]- W. x- 4+ years experience in the semiconductor industry in relevant R&D departments.  
' s$ v, \6 i0 X! F3 r' _* M- Preferred to have at least 1 successful tape-out experience as project manager  
8 R# M3 D3 F" o. p- Knowledge of ASIC Design from front-end to back-end (Analog design, RTL, Synthesis, STA, floor-plan, P&R, package, testing, etc.)  
% Y$ S0 L( Z; ~! G- Basic leadership of team for allocation of tasks   
4 ?! G  e: F9 A  P$ }- Management experience with subcontractors  
/ N: i7 j# O; @- `6 @) g- Good English, excellent communication skills and team spirit oriented  
3 {: h. b" @% L- Self motivated, strong communication and interpersonal skills
作者: tk02561    時間: 2013-11-19 09:00 AM
ASIC工程师
( F' I; Q* q; ^公      司：High-technical IC supplie with commercial FPGA intellectual property
( r0 G3 j3 ~& `5 i) F5 O工作地点：北京
( i- d$ m  t8 n+ ]6 r" U' x& C9 Q! ?
职位描述
4 E1 N! y$ @4 q+ Q: g1.微电子相关专业硕士学历, 3+年ASIC前端工作经验（不含在校、实习）;  5 {" n% a9 a+ ?" W# H" z
2.熟悉并参与过ARM或MIPS等常用SOC架构的设计、应用,对SOC架构及常用外设的工作原理有深入理解。 0 `7 L9 W$ O) e
3.精通verilog语言，能够独立完成verilog module design，拥有良好编程习惯codingstyle。 $ T% a4 L" x3 j* X8 r6 L
4.能够独立完成单元级仿真，在系统仿真中承担部分工作。
9 Y, E( W) Z7 T8 B5.至少1次成功流片经验。 : O9 h& t- ?& x1 K; {
6.对synthesis、sta、dft等有一定了解。
; j: {0 l6 T/ a; q' L4 J7.良好的团队合作精神 3 f+ b4 Y1 r& z* D* y, n" G% x

' e7 ?: Y2 S8 A4 g* P; g. N* q  K职位要求
% F! I* C/ m. y. @全部或部分满足以下条件者优先考虑：
* H' n$ a; u& q6 a; y5 }! W. v1.有在大型asic公司工作经验，深入理解其企业文化。
2 h$ i1 B5 ^6 `2.熟悉验证方法学;熟练使用SystemVerilog等专用语言进行验证平台的搭建和维护。对Testcase规划、覆盖率分析、门级仿真、ATE testpattern产生等有实践经验和深入理解。
% P$ Z, F3 t3 ~9 v3. 丰富的fpga emulation经验，能熟练进行板级debug，编写调试简单driver。
+ W, ]2 }4 D/ K4．对芯片系统架构有一定理解，能进行子系统级别的独立规划设计。对以下知识中的至少2种有实际经验： ( T; O$ x1 y/ x4 Z" N! B
ARM/MIPS/8051 CPU及其架构, / Q# b; }- T! \6 g
AMBA(AXI/AHB/APB) 总线、OCP,  9 `* c  `& N& V
USB(3.0/2.0/1.1,  
, |2 Q/ a: x# w  S. ^7 S0 \NAND/Nor Flash/S-flash controller " k+ N# ]  l2 R6 ]: O" K
DDR（2.0/3.0）controller/PHY
! f3 p/ W# D0 r% ^% m0 H( Y& ]9 Slow power design,  
: t1 ]9 |- h8 }chip level clock/reset generation and control,  
- x  I5 v3 e. YSD card controller, SATA,sim card  
+ k' D7 \: }$ asoc基本外设 (SPI/ GPIO/timer/WDT/I2S(SSI)/I2C/UART),
' ~% z; \) p0 u* Q; CEthernet,  
+ Z+ W9 s; B9 ~7 N8 Z: gJTAG, etc.
作者: ranica    時間: 2013-11-26 09:32 AM
ASIC Digital Verification Engineer
2 B) _; t: `- Z' W' @4 A7 o+ H
! `; U4 ?1 f1 e& c' a% r6 h公      司：A mobile chipset semiconductor company
! P' K, D- z2 l5 v工作地点：上海
- E" G5 @: c" D" b
& O/ r8 w# R& oResponsibilities:  
- j! V$ y# H8 ]5 I( @9 \  Make verification plan for one module or whole chip.  1 ]2 o4 @8 X; m, N5 D' `/ o
  Build up and maintain module-level and chip-level verification environment  
* _/ W. ~4 e, ~1 \  Verify ASIC digital design based on case list, and output verification report.  - ^) r. t1 c1 F- z, c
  Also responsible for lint checking and formal verification.  
$ Y" Q4 T" F1 g9 m& d7 Z- y+ B0 z) r0 N( M7 T9 d+ ~9 l
Qualifications:  
& X; O( k2 e( h1 G3 a4 O  Proficiency in logic verification.  - |$ l* c7 Q& e, ^' u) k+ z
  Experience with Verilog logic design language.  
. f3 z% x0 B) C" m  Experience with high-level verification languages such as System Verilog, System C, Vera or Specman e language.  8 N1 u( y4 l! c! N+ G% D+ Y
  Experience with UNIX/Linux simulation tools such as IUS or VCS.  1 F/ `0 L+ g# k- u: \6 r( q
  Experience with C and C++ is a plus.  4 G: ?) x& z' y$ h# r* W7 K# c
  Experience with C_SHELL, TCL or PERL is a plus.  
: h9 L6 h, ?6 o2 Y( f& m  Experience with UVM, OVM or VMM is a plus.  5 c9 E: U3 ~( l
  Good knowledge of SOC design is a plus.  
5 ?0 O8 B7 b' O+ T# k  G! Y5 _  Good knowledge of software design is a plus.  
# m1 _) }* o5 g% b* O8 M. p8 G9 m  Self-motivated and good team player.  
3 N8 R3 s+ |' P; o( W  W  MSEE or BSEE with 2+ years.
作者: ranica    時間: 2013-11-28 09:28 AM
数字芯片设计工程师（DFT/综合）
; G1 q" P3 l7 E5 o9 Q: S: o& G9 x! Y% C
公      司：A mobile chipset semiconductor company$ {& s4 u2 b6 U
工作地点：上海
$ L/ g' D4 F4 C* N6 y* n. P6 e$ ]& F! w. ~" \+ u& m
职位描述：
6 {9 ]: E: w) p( W3 u1、To provide and support SYN&DFT work for several projects in parallel  
0 w* N9 @3 `5 U" P' z1 I4 D# f6 m2、Run block level implementation for each project, include synthesis, DFT and LEC
7 u1 T  h( @1 T% X/ P# L! z7 n3、Support block level physical evaluation  
7 Q3 T9 C7 ?1 Z+ j4、co-work with designer and provide block level SDC file ) Y  ?! Z0 t- Z: b  ^% q" x2 O/ u' g
5、co-work with Back-end team for timing signoff
' e& s1 u, ~: j9 g; h+ c- M0 h/ M( O0 p0 c) U: M! V+ ~
职位需求： " N& a! K7 ]6 T7 _
1. 了解集成电路设计的基本流程
3 G( J- E1 @6 {' Q/ _1 q2. 相关Synthesis, formal check 和DFT的工作经验。(3A, 3B, 3C精通一项即可) 5 e/ K% z2 M  c8 q0 H( @) K, _9 [
3A. 有超过2～3个项目的synthesis 经验， 用过RTL compiler且熟悉timing的相关知识  % P( K" w" v, B9 l" ?
3B. 有超过2～3个项目的formal check经验，熟悉CPF的low power flow
$ O7 L, ?4 h, e2 t& G. a3C. 有超过2～3个项目的DFT insertion经验， 用过Mentor DFT的优先考虑 ' @  L: e0 P$ E+ t+ ?
3. 具有良好的英语阅读和书写能力。
作者: globe0968    時間: 2013-11-29 01:38 PM
IC PM# V) k! o8 z! }( D; ?
公      司：A famous European IC company- E0 E2 S, I0 k- d8 s
工作地点：上海' D1 F. e; k" A* h* \
$ F' C* e- \# a3 u
Roles and Responsibilities   & q2 N) K+ V- ~0 x6 ?- |; y
1. Manage ASIC design project according to product development process   ) k1 B' X" c! o" c) l' g3 i
     - Coordinate the different resources to deliver the ASIC product in time and with good quality    a- h4 u( s; ]% b; T
     - Responsible for the communication of the whole project team  ' O7 P9 M: h) M0 Y$ r3 U) l
     - Participates and drives internal review of each development phase and make proper justification  
9 q6 U* x0 V3 a) m     - Develop and manage project schedule, resource, communication and critical path  $ }# s( q5 k. C/ ], s
     - Identify risk and develop mitigation plan with the project team  ' |& S" M: F5 f5 l
2. Closely work with IC manufacturing and testing / qualification to drive the ASIC products into mass production in time and with good quality / l% b3 Q# x* W+ a( v5 g
3. Work with the financing and control the project budget
- |/ ^; w! d* ~' Y& o. W, _4 o- m( C6 d- H8 I2 G
Qualification Requirement   ! z6 n: l5 N8 D, H* k; f2 b& v
- Master degree or above in Device Physics, Electrical/Electronics Engineering or equivalent  ) M8 w  ?, K+ h: t2 t
- 4+ years experience in the semiconductor industry in relevant R&D departments.  * v+ T) Z% G+ M5 g1 z/ c3 h; ]
- Preferred to have at least 1 successful tape-out experience as project manager  
7 R( j: a1 |$ D( D- p- Knowledge of ASIC Design from front-end to back-end (Analog design, RTL, Synthesis, STA, floor-plan, P&R, package, testing, etc.)  # \8 i( V) e8 I3 i" j4 r+ ]
- Basic leadership of team for allocation of tasks    3 ?: L' {- p0 q% X: Y
- Management experience with subcontractors  
+ S+ k3 p" E- I1 n6 F# r" }( }- Good English, excellent communication skills and team spirit oriented  
- a8 p% g0 C+ |7 k# r# o7 T- Self motivated, strong communication and interpersonal skills
作者: ritaliu0604    時間: 2014-1-15 09:44 AM
数字芯片设计工程师（DFT/综合）# g  e5 V2 N0 J3 B& B' k0 P
公      司：A mobile chipset semiconductor company
$ [) F! A+ p3 H  ]+ d. E工作地点：上海; ?2 r8 x, z. ^1 y- O. t7 C) O

* q/ R' h4 u2 [职位描述：
$ J7 @6 R5 S' i* H, c1、To provide and support SYN&DFT work for several projects in parallel  
! t3 ^! U- e: W$ N5 P* `2、Run block level implementation for each project, include synthesis, DFT and LEC
2 C+ A; j. A+ _3、Support block level physical evaluation  - C# N4 z# o: N7 P' C9 g8 i
4、co-work with designer and provide block level SDC file ; l+ @8 O) D4 D- v4 z6 N! ^1 b5 N# i
5、co-work with Back-end team for timing signoff
! \5 e8 B, `+ `, f, e0 e/ Y2 s$ M$ S8 L
职位需求： / V9 h( F3 `, G) y8 ?8 P% q
1. 了解集成电路设计的基本流程 ; X4 M4 V# S6 j9 d8 p6 i
2. 相关Synthesis, formal check 和DFT的工作经验。(3A, 3B, 3C精通一项即可) & I+ x% x: W1 ^4 r+ N
3A. 有超过2～3个项目的synthesis 经验， 用过RTL compiler且熟悉timing的相关知识  ' h1 o! G6 Q- j
3B. 有超过2～3个项目的formal check经验，熟悉CPF的low power flow
: B9 S; e0 F) v" v4 }/ o& v3C. 有超过2～3个项目的DFT insertion经验， 用过Mentor DFT的优先考虑 ' L* r% A1 h. g
3. 具有良好的英语阅读和书写能力。
作者: ranica    時間: 2014-3-6 02:28 PM
资深数字IC设计工程师（图形图像方向）. _1 Z( e2 c1 S+ U4 h  m
公      司：A famous IC company
& j2 ]. v+ q9 A7 \3 w工作地点：上海1 V/ X0 D. D, n( c  a

. w6 `( k0 Q7 H岗位职责：(图形图象处理和视频编解码方向)：
8 b" S, y1 M7 T6 w) T% z: k1、根据市场需求和芯片定位，参与并带领团队完成图形图像处理或视频编解码等复杂IP的设计验证和交付； 3 P- j$ W* w. W) V( m# P  }0 i7 j8 X
2、对项目进度和质量负责，组织具体技术难点或紧急任务的讨论和攻关，协调其他团队共同完成SPEC的制定和收敛； + k0 b9 O2 B+ y# ?

# T+ W( X+ p5 S岗位要求： , q+ }- }6 l8 [- g: p
1、硕士及以上学历，电子、通信、计算机或微电子专业；
6 R6 V0 m5 I' G$ V5 E( I8 A0 a) c2、有至少两年以上图形图像或视频编解码等领域的IP设计经验；
, E8 A" A, w' q1 U, f3、具备丰富的图形图像处理或视频编解码等相关领域的系统知识 ' Y) _% |% R. ?  @
4、具有扎实的数字芯片设计基础，熟悉IC设计的整个流程； 8 }+ L' b$ x0 D& s5 _) U
5、具有良好的沟通能力，较强的协调能力，以及团队合作意识；
  `6 U9 a1 @6 u6、有团队管理经验者优先考虑；
作者: ranica    時間: 2014-3-6 02:28 PM
数字IC设计工程师' W. [; H- Z9 z3 i
公      司：A famous IC company: j7 F! u6 }' _: o; t9 s  @' P
工作地点：上海
; a  d  i; X+ a7 x0 ?9 z% I# g* s7 M
岗位职责： ( Y6 h0 m. J: c1 J1 _
负责各种IP（图形图像接口、图形图象处理、视频编解码、DDR存储接口、Flash接口、USB接口等）的设计、时钟复位模块的设计或者SOC相关的集成设计、系统设计、架构设计。
. S6 i" X  s, x" |2 V9 V' H! D
- E; x1 R; l0 h& r/ w5 N' }职位要求： 4 g6 b' @# z9 l
1、硕士及以上学历，电子、通信、计算机或微电子专业；
& r+ i& q4 m; t, N+ `  W, L2、熟练掌握Verilog、SystemVerilog等语言的编程，有扎实的数字电路基础；
1 \* O- D$ l* i5 N# h. J! h5 c3、有1~2年的相关工作经验； - N. |0 }  h1 G, [' w; x; y
4、具有较强的学习能力、沟通能力和良好的团队合作精神； ( V- a, l1 u. R4 V
5、在以下相关的模块或接口（其中之一）有一定的工作经验：图形图像接口、图形图象处理、视频编解码、DDR存储接口、 Flash接口、USB接口等 0 Z$ L/ ]9 _8 X0 k3 b8 x; K. U
6、有大型SOC芯片的研发经验者优先考虑。
作者: ranica    時間: 2014-3-7 01:12 PM
Sr. Staff to Principal Engineer/Mgr
9 W( K* F: o8 j) x3 R2 B公      司：A famous IC company: [0 N, T% a+ \* ^
工作地点：上海
' J% z1 j! V% K$ S$ C1 |3 l2 M2 [0 A+ X. m, J$ P, A3 Q2 J4 a
Job description
# T9 F  O& D  xThe candidate will be responsible for the architecture and ASIC design and co-verification of various 802.11 wireless baseband IPs within current and next generation wireless products. The candidate will work within the local DSP/digital development team and closely with system/simulation/verification/RF engineering teams in US to develop and implement DSP/digital blocks to build WiFi IPs.
  U4 z/ G3 U) N% q% p% b
- y# ?9 _3 c9 R5 XJob responsibilities includes: spec development and design of DSP/digital blocks, developing co-verification platforms, performing simulations, and solving integration and testing problems during the development, characterization, and production stages of the product. Successful candidate must have the ability to communicate with engineers of various backgrounds: systems, software, digital hardware, RFIC design, and verification
作者: ranica    時間: 2014-3-7 01:12 PM
职位要求, g% T# O3 q/ {, @( c: `6 |
?Extensive hands-on experience in the development of WiFi baseband IC design. The candidate must have at least 8-years development experience on WiFi 802.11 a/g/b including minimum 3 years on 802.11n/ac.  
& Z% W7 x$ E& Z2 I& c?Deep knowledge and good understanding of: digital communication theory, information theory; specifically on: equalization, Fourier transform, spatial-temporal coding, linear and maximum-likelihood estimation, Viterbi decoding, frequency/ timing estimation and calibration, automatic gain control, transmitter beam forming, diversity combining, and their high-speed DSP/digital implementation.  ! U7 X& K7 T9 t, k
?Extensive experience with RTL programming languages.
2 }8 Q( L! B' @: j" C" v: c?Experience with verification methodologies and tools and advanced complex RTL/C test-bench developments. The familiarity with UVM environment is a plus.
, S: }" @  H+ b' Q- B. f?Experience with developing algorithms in C, C++, and Mat lab.
1 v; g  l8 z' w6 e2 O2 f?Experience with scripting language such as Perl, Python.
% L  \/ F; c  K: j7 x3 ]?Must have experience with lab testing and characterization of digital sub-systems. - o, [& j" C. Y8 u( m( u! L
?Candidate must have strong English communication skills with willingness to interact with various groups within the company.4 Z4 V6 P/ l. n/ u4 \2 G: v! w
?Experience with physical design flows, tools, methodologies, and development of timing constraints is a plus.5 M# }3 z* y8 r- Q7 \
?Familiarity with flows and tools for co-simulation of RTL and C models is a plus. 7 `1 @) M2 N7 \! D* ]
?Familiarity with testing and integration of RF and baseband systems in the lab is a plus. 6 V5 F. f" W0 O# a
?Experience with implementation of calibration modules for RF/Analog blocks is a plus..
" I3 x" H4 D' j2 d?Typically requires a Master degree and 8 years of experience or a PhD and 5 years, in VLSI/ASIC architecture design or ASIC implementation of digital signal processing function.
作者: ranica    時間: 2014-6-4 09:13 AM
Senior Digital Design Engineer/ s5 A" L2 O0 \5 ^5 k

4 h$ O( J. P: |8 Y( u9 p2 U公      司：A leading semiconductor company* L5 p. A) A$ ~3 ]8 P. ]8 S( C
工作地点：香港, V% P, _% |, u
! Y, `# ~6 o, k- I( h1 U
Job Responsibilities:
! R4 T% ], a" z$ _5 ~! d; K! p    Perform logic design, RTL coding, design verification, logic synthesis, DFT and static timing analysis
3 o; W5 i% n8 C) n    Develop verification environment and coverage closure ' _( s/ h8 O: L9 |
    Support wafer level testing and silicon evaluation
/ v; [9 W/ d( C3 _    Prepare technical documents
9 e7 [1 S( o+ z: Z) i" x# Y. W# Y4 j+ X& d. ^
Job Requirements:
/ [  l1 M- B1 v1 V9 y; D8 Y/ d    B.Sc or above in Electronic Engineering or equivalent. Applicants with postgraduate degree would be considered as an advantage
* m" X. }5 b0 a( U    5 Years or above of solid experience in one or more of the following areas: Verilog-based logic design and synthesis, constrained random    testbench with System Verilog & UVM, assertion based design verification or circuit-level SPICE simulations
% X+ E# s$ j$ ^+ S9 _    Knowledge of SoC and embedded system. 8 P5 Y, S+ w- [  U% O) C' {2 V
    Knowledge of scripting languages such as Perl, TCL and Make # ?( S1 D# L! I! \" }9 s
    Candidate with less experience will be considered as Digital Design Engineer
作者: mister_liu    時間: 2014-6-12 10:46 AM
Junior Physical Design Engineer
3 |" z7 r7 w5 i# a* `6 C* J6 S
& f9 l" G# k( V: g/ X6 w公      司： famous IC company" ^. b3 K/ `0 S$ \- d9 e: D0 z3 S1 S9 y
工作地点：北京
; X: f" z/ |; H- A( \& v
- q) E- B3 X' k0 a5 tPosition Tasks, Duties and Responsibilities . L0 `# L. q" Z, E3 Z: r) J
The ASIC Physical Design Engineer will: & r' G* q( S' I9 H
        Complete third party IP integration and ensure vendor guidelines are followed. , t+ {' z) E6 U, r! Q  A# ?3 V
        Responsible for physical verification (DRC/LVS).
- X+ P8 E' M3 K8 p; b2 Y+ s. O        IO ring design, fullchip floorplan. , x% j( h4 b' h- {$ Q3 P: Q/ Y4 A; I2 s
        Block level implementation.
" d* H; ?) o! Y& y/ T  w        Work with front-end engineers to resolve problems and achieve design closure. 6 m: L) d6 `9 ?, z1 i( x9 ?0 w

# `, F+ F8 [! qCandidate Qualifications:
: a$ ~& e" {/ t$ pCandidate must:
& c* F; D" Y, o8 j1 {7 f        Hold BSEE (MS preferred).
! a* i) Y& X0 O3 d0 l4 [3 T7 ~1 o        Have minimum of 3 years hands-on experience in full flow IC back-end physical design and verification
, w3 f$ Z7 l' x1 u( n7 D' a/ V7 P% p* h        Be able to complete block and chip level tapeout quality LVS and  LVS and DRC. " A: y, Q8 c% {: P  h
        Have the ability to independently identify and resolve design, tool, and flow problems. 6 }4 |0 S6 U0 s+ O& V
        Have related timing and physical concept. ( v- [8 \) B& b+ \
        Be able to design and implement physical design strategies and methodologies for deep submicron designs.( N8 G0 a# B" |0 o& }0 s2 w
        Familiar with EDA tools. ) e$ `0 }6 [7 ^4 s# s& l% t1 O8 p
        Familiar with Linux environments.  2 B2 k) W: D' |2 K

2 o6 Y, G* U5 P- m: w: K4 r  K6 f# G3 JAny of the following is beneficial:
5 {0 q- b% b. s9 Z2 s        STA constraint design
: I4 p& D5 J- i. V       Equivalence checking ?RTL to gates, and gates to gates.
作者: ranica    時間: 2014-6-19 09:41 AM
Junior Physical Design Engineer2 l" A/ E8 t+ y4 i0 F" y1 @" h
8 D( r7 L; l  _0 A9 g8 q
公      司：A famous IC company
$ {! L0 H( v1 A' x, J工作地点：北京
' m7 ^1 f/ w9 g8 a% y% }) T/ Q% J1 m
Position Tasks, Duties and Responsibilities
2 N2 e9 O' t8 |* ]8 r2 rThe ASIC Physical Design Engineer will:
& r* ]6 j6 `& L1 G: G$ ^( G2 @        Complete third party IP integration and ensure vendor guidelines are followed.
; |6 F' E  r* X8 F+ [) f' ]        Responsible for physical verification (DRC/LVS). ! J# `) @5 U; M
        IO ring design, fullchip floorplan.
. @, O" h* s; R        Block level implementation. & E  n8 ^8 i; j4 p- x9 |  T
        Work with front-end engineers to resolve problems and achieve design closure. 5 V  i7 O; K. `4 P1 A

2 l! {  ?6 t; g3 `' C. JCandidate Qualifications: 4 m7 t3 n( S  V. j( c0 e
Candidate must: 0 P' D2 t- B+ q
        Hold BSEE (MS preferred). 2 |3 B6 H' W) K" g+ @7 h/ T2 H
        Have minimum of 3 years hands-on experience in full flow IC back-end physical design and verification # A6 S! O2 t- u' {3 f( z! v
        Be able to complete block and chip level tapeout quality LVS and  LVS and DRC.
6 W* l: {. ~" K: O. q        Have the ability to independently identify and resolve design, tool, and flow problems.
% S( r: Z: R  ^3 r2 f: H. k: L7 |        Have related timing and physical concept. 1 ?- l0 v, q: [& u+ U$ x
        Be able to design and implement physical design strategies and methodologies for deep submicron designs.' @3 J- [4 z; U3 R" V6 M" F
        Familiar with EDA tools. : {: k5 j9 h8 s5 t- r9 `+ |
        Familiar with Linux environments.  
' t. B; K" N9 O) Y% Q3 h9 o1 @6 P4 m5 {9 Y+ ]+ {+ \5 p9 L0 b& \: }
Any of the following is beneficial: 1 ^7 _& B# X0 o9 {
        STA constraint design : V0 I" |" `/ i. i4 O
       Equivalence checking ?RTL to gates, and gates to gates.
作者: ranica    時間: 2014-6-19 09:42 AM
Sr. ASIC Design Engineer (encoder/decoder)% E# J- S: T1 r* }  _# a
- J6 u6 l; K' o9 k( P0 i. z4 T3 A
公      司：a leading developer of advanced digital imaging solution1 F0 m) Q* j, e" l5 X' c
工作地点：上海
6 f. C9 h* q+ N* U4 ^( E$ }$ r2 A4 }0 k% c- y
Position Overview: The candidate will join a team of  highly competent ASIC designers involved in design, verification, and implementation (ASIC) of advanced platform for XX''s future generation multi-media products.   4 d" _: w2 x/ }5 I% H

( w0 S% Y% y, a" O! d( N主要职责 (70%) + M! T, r( d# J  p
In-depth knowledge of TV encoder and decoder design. Good understanding of TV system design.  % y$ z: z, _" ~8 g3 Y$ k% u. D
Proficiency on digital filter algorithms and hardware implementation. " E0 f7 c/ |7 k
Development and verification of complex IP module, integration of the IP module into the Soc devices, top-level design handling, system level testing. / x/ o' E, I9 ?3 J0 m
Participate in the FPGA platform development and lab debugging   * L, h  b9 f2 ?8 B$ d% [

( c! q3 k% M: [" k  T% r/ S6 J/ G3 X其他职责 (30%) : D: c' c( x* m; M0 {
Participate in block level architecture design Assisting embedded FW development.$ m/ E1 z' f+ x8 F7 s% g, @
职位要求$ s. y6 d& A7 `
岗位资格
* w6 r) `! w) f" g8 A" ]经验/技能
! F. a' h- F( d0 ~1. Strong knowledge of TV technologies, knowledge of image signal process and CCTV system is a plus $ v: x5 ?' Q! }1 m2 X% r# Z4 u
2. Strong knowledge of ASIC design flow. Can define Micro-architecture of the IP module and /or sub-blocks. And able to write detailed engineering specifications. + `* o3 r4 Q0 ?9 S* D
3. Good communication skills, especially in technical writing and reporting;
4 o, \* p6 y. _- P2 _4. Self-motivated and ability to excel in a team environment.    / X( t9 [- `2 S! ~7 r& e6 n

3 H. Y+ ?1 Q+ X; N教育 ' M) @' B* A, u% U
MSEE/CE with 3+ years of industry experience
作者: amatom    時間: 2014-6-20 09:03 AM
Senior Digital Design Engineer
3 x& |- n7 v; U% N
+ o7 D9 ~% I4 s4 I+ Q" u% r; U! r公      司：A leading semiconductor company* N6 |2 p3 [3 h. h' ]0 z  R. G% n
工作地点：香港1 D8 j3 l3 U9 b1 |5 q5 X# N
. Z* S4 d6 b1 a" s, @
Job Responsibilities: : Y; ^# W( r3 |' Y
    Perform logic design, RTL coding, design verification, logic synthesis, DFT and static timing analysis , U" q2 ]% _* T
    Develop verification environment and coverage closure ! @) U; S$ L4 f7 O
    Support wafer level testing and silicon evaluation
/ [, K" A: o" V2 k& W' N    Prepare technical documents
3 i, ^. h6 s9 K& \+ K8 x  i3 W& p
/ S0 u4 \/ E3 D& MJob Requirements: 6 N. b5 A8 {/ }& W  I" \: b
    B.Sc or above in Electronic Engineering or equivalent. Applicants with postgraduate degree would be considered as an advantage$ ^5 Q: X4 V2 W
    5 Years or above of solid experience in one or more of the following areas: Verilog-based logic design and synthesis, constrained random    testbench with System Verilog & UVM, assertion based design verification or circuit-level SPICE simulations ) ]8 O  o% \; j4 e. j, V; m
    Knowledge of SoC and embedded system.
4 K  G$ V6 e! A, `% U& E6 T    Knowledge of scripting languages such as Perl, TCL and Make
8 v' ^9 k' w. S3 S9 w2 X    Candidate with less experience will be considered as Digital Design Engineer
作者: innoing123    時間: 2014-6-24 11:57 AM
Junior Physical Design Engineer
. r& c4 s) n7 S/ W% k1 N0 a公      司：A famous IC company
3 W! N& p# g* D# U* r工作地点：北京* B/ P$ q+ z, K7 }
% Z! g3 R* o$ b/ U7 f5 Q# L& {
Position Tasks, Duties and Responsibilities
. n* N  N1 r6 e4 }The ASIC Physical Design Engineer will:
& n- Y' k* C# S: Y) E* |4 C, P        Complete third party IP integration and ensure vendor guidelines are followed.
( x4 G/ n1 ~6 _& e        Responsible for physical verification (DRC/LVS).
9 b; Q8 }7 E( B4 X        IO ring design, fullchip floorplan.
( ^5 q* ~; n0 |8 @- Y" ~        Block level implementation. $ ]: t$ G" j  U: G; |( d
        Work with front-end engineers to resolve problems and achieve design closure. $ t0 `. ?4 Y& I9 P* S
# Q2 b7 v" X/ ?! j
Candidate Qualifications: 7 a3 B# m9 M( o1 I
Candidate must:
4 j& k/ ^6 k- J% T' U: }        Hold BSEE (MS preferred).
  l5 F$ o+ Y$ I0 W+ z        Have minimum of 3 years hands-on experience in full flow IC back-end physical design and verification
' {' C3 J7 j6 x. c        Be able to complete block and chip level tapeout quality LVS and  LVS and DRC.
% \9 K2 ]; a0 J" O& r        Have the ability to independently identify and resolve design, tool, and flow problems. " [& k) `* p1 K$ U! o
        Have related timing and physical concept. 6 _! O0 r" M" H
        Be able to design and implement physical design strategies and methodologies for deep submicron designs.
$ O- K6 s0 L/ @        Familiar with EDA tools.
! F: G' l: I6 o" p; I0 _2 U        Familiar with Linux environments.  
8 G' ?" G. K' i9 a1 k! I3 J+ [% [: J) Q  t4 F) m' I& r) t
Any of the following is beneficial: ' f& C) z. W7 t
        STA constraint design
: g6 j6 P/ h* {6 C- A       Equivalence checking ?RTL to gates, and gates to gates.
作者: ranica    時間: 2014-7-31 12:31 PM
数字芯片设计工程师（DFT/综合）2 @# p1 Q9 ~/ P- U
: P: m4 e( m$ X9 V
公      司：A mobile chipset semiconductor company
/ p: d& ^' J/ k! |! i% ^工作地点：上海* A0 S$ H; v$ P+ z

- j5 t) A8 t3 y7 F* f1 R$ c职位描述：
5 [, [$ ~% L/ S; p: r! q1、To provide and support SYN&DFT work for several projects in parallel  
& K* Q2 x, E) S. b2、Run block level implementation for each project, include synthesis, DFT and LEC
' j' C( V% Z( r2 `" Z# c7 h1 y! a( d7 s3、Support block level physical evaluation  : W* ^( }) L" d  l
4、co-work with designer and provide block level SDC file
! c- r* l. ]! L- _6 v7 H8 N5、co-work with Back-end team for timing signoff9 F$ ^: ?  C/ ?1 K+ Q! i

5 c1 ~# F! G  B! L) r8 U7 ]职位需求：
1 \( o2 }  i& j( @3 `  m& U- c; C1. 了解集成电路设计的基本流程 2 u: m$ p( i: A& X; B4 U; R+ G- }
2. 相关Synthesis, formal check 和DFT的工作经验。(3A, 3B, 3C精通一项即可)
, G9 G$ C: t" z2 O3A. 有超过2～3个项目的synthesis 经验， 用过RTL compiler且熟悉timing的相关知识  8 C; }0 d' M: n" [7 V1 R
3B. 有超过2～3个项目的formal check经验，熟悉CPF的low power flow - v4 H; n) u5 B; a+ e, C$ N* y
3C. 有超过2～3个项目的DFT insertion经验， 用过Mentor DFT的优先考虑 ; N& V, |3 t% l% o( i
3. 具有良好的英语阅读和书写能力。
作者: tk02561    時間: 2014-10-29 08:13 AM
標題: ASIC Corporation將展示節能、高頻寬效率的C-RAN解決方案
西班牙巴賽隆納--(美國商業資訊)--eASIC Corporation：
& }7 e  m: W  y+ k7 x1 U8 j# N( v, F4 c, R' Y7 k+ i: ]; I" I
人物：
) I3 L" a# V; q7 M6 {" @# R* a3 K' }( W/ m8 _1 R* j
領先的單光罩自適應ASIC設備供應商eASIC Corporation將由eASIC無線業務主管Christian Lanzani博士擔任代表，負責整體無線策略，包括無線存取、去程傳輸(fronthaul)連線、基頻處理和回程傳輸解決方案。
9 {4 \) f! o2 u" R; M3 k8 n! L
9 E6 v. l5 g( ^, Q" {; a事件：
2 y& \. E) I  k% m! U# E/ E0 w1 f: P* a; u4 J% h( w1 t0 D
eASIC將作為聯合贊助商參加Wi-Fi世界高峰會、去程傳輸暨C-RAN高峰會(Wi-Fi World Summit & Fronthaul & C-RAN Summit)，展示C-RAN去程傳輸在部署方面的挑戰，提供eASIC解決方案的細節。展示過程將包括無線存取、CPRI over OTN轉換器和基頻集區，包括L1硬體加速的使用案例。
( a/ F5 Q$ N. ~6 {6 ^+ C4 n
2 @* n- ]" [2 D7 f時間：2014年10月29日，週三 * ?& t5 x& V5 v  q9 q. }4 E
地點：西班牙巴賽隆納赫斯珀裡亞塔樓酒店(Hesperia Tower Hotel) % P+ H1 j3 T2 v- [& N

8 l. C' R2 D0 |: W( l9 E' x如需瞭解有關eASIC Corporation的更多資訊，請造訪www.easic.com。Wi-Fi世界高峰會、去程傳輸暨C-RAN高峰會細節可以從以下網址獲得：http://wifiworldsummit.com/。 3 g9 M& q6 \$ Y+ d0 T

% V- I& K7 \0 |8 l關於eASIC
: P3 e, V4 N/ W! c
% l5 }( U% z; @0 Z7 m$ Y& IeASIC是一家無晶圓廠半導體公司，提供突破性的單光罩自適應ASIC設備，旨在顯著降低客製化半導體設備的整體成本和縮短投產時間。使用通孔層客製路由的專利技術實現了低成本、高性能和快速周轉ASIC及單晶片系統設計。這種創新構造使eASIC能夠提供前期成本顯著低於傳統ASIC的新一代ASIC。eASIC Corporation是一家私人公司，總部位於加州聖塔克拉拉。投資人包括Khosla Ventures、Kleiner Perkins Caufield and Byers (KPCB)、Crescendo Ventures、希捷(Seagate Technology, NASDAQ:STX)和Evergreen Partners。如需eASIC的更多資訊，請造訪www.easic.com。
作者: CoCo3646    時間: 2015-2-23 08:44 PM
Asic 的利基市場和 Fpga的利基市場 各有千秋.
# n9 k) E  V2 e
作者: fgg633    時間: 2015-7-23 09:32 PM




歡迎光臨 Chip123 科技應用創新平台 (http://www.chip123.com/) Powered by Discuz! X3.2