標題: 靜電放電測試 [打印本頁] 作者: ritafung 時間: 2008-4-12 12:55 AM 標題: 靜電放電測試 剛剛研究了靜電放電（ HBM ＆ MM） JEDEC標準，實在需要很長的時間去進行測試。假設該IC具有數以百計的pin，很可能將需要超過1個月完成整個測試。這裡是否有任何人負責做ESD測試？作者: m851055 時間: 2008-4-12 08:07 AM
竹科閎康科技有此業務" U) A* N! \, w/ m2 X. D
電話在網頁就查的到了.......................作者: cuban487 時間: 2008-4-12 11:12 AM
很多實驗室好像都有,但都在台北.5 c$ K( s9 K' j
儀特好像就有可以去查ㄧ下作者: kyyyyyykimo 時間: 2008-4-16 01:02 PM 標題: 很多家實驗室都有啊 目前新竹地區有"宜特"與"閎康"兩家比較大$ V/ j; ?2 y- K( K6 k
我的建議是去閎康，會比較適合。 2 t: v2 c" p; Z# a% |2 `6 b因為我本身工作性質也是有接觸到ESD測試 + F& h, T% Y4 Y9 M' @測試多Pin需要花費時間比較長久，可是你們HBM是使用JECDE! X: {% D4 w: X ]
在Zap的次數明顯比軍歸來的少了。 ' @5 _ F- ^$ p! \3 a作者: ritafung 時間: 2008-4-22 12:07 AM
my company is pursuading to MIL-Std ...6 X0 M3 ^& |6 Y- `
actually any company need MIL-Std? Our application is not for military purpose....作者: wesleysungisme 時間: 2008-5-21 12:14 PM
For ESD test (HBM)( U( o. M9 r3 s* [1 n& l' O. O2 J
The following are the test combination:0 @# D2 {7 }, H3 f/ E$ s# f3 D
1. Power to Power) b2 z6 ]: E" F& N) j3 b
2. Power to Ground7 A/ a, C) Y: R* G
3. IO to Power7 D9 W, p) J0 L& R( o) L4 T2 O7 z+ r
4. Io to Ground5 o+ u( b( q; j7 `7 V4 E* _
5. IO to IO; J2 f* K+ Q6 h% S3 j6 [
(different power domain need to be treated as different power. For ground usually you can treat as one group_silicon use substrate as common ground. But if you measure two different ground pin/ball > 2ohms. It should be seperated as 2 grond.) ! e% t0 m. k6 R - r6 m5 W% A" s6 g- N+ [: _( @+ Wthe total zap time fomula will be~ 2(+/- polarity) X (IO#X(P#+G#)+IO#+P#X(P#-1)X(P#-2)X...X1+P#XG)% s$ P, P1 v( _9 U W$ u3 x
For example: You have IO1/IO2/IO3/P1/P2/G1 / w. @, v/ z" r- Y6 X" ]" i6 a2x((3X(2+1)+3+2X1+2X1)=25(multiple the zap interval)1 [5 d1 p9 }1 K! d' d
So for high pin count it will take a lot of time. But it won't take more than a week(for one chip). * `" _; m7 a5 b: [' k) ? % X: E: M* N0 {' d- oFor your reference.作者: f5882077 時間: 2008-5-23 03:02 PM
樓上的Jason...據我所知大部分的IC設計都會跑去宜特做ESD...為什麼你要特別建議去閎康做呢?? , I4 a7 O. F: Z$ ?有什特殊原因嗎??會比較適合的邏輯是什麼??是否可分享一下心得??感恩~作者: ritafung 時間: 2008-5-26 09:15 PM
thanks wesleysungisme for your answer. 7 [9 C' t" k6 d) bas our pin count is over 1000 and no. of power is ~ 20, so it's quite time-consuming. 6 G+ j, F$ ~$ L% t: kand there is technical issue about bonding all the dies into COB for ESD zapping, i wonder if anyone could share their practise? we feel difficult to strictly follow JEDEC standard.
