標題: 關於Design Vision的問題 [打印本頁] 作者: 小人發 時間: 2008-3-27 09:14 PM 標題: 關於Design Vision的問題 用工作站跑verilog的時候 # W# |& H4 c6 L7 J7 F" G在DV的階段 出現了一個警告4 Z) d4 v4 [! E; r# f8 u2 M& r
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Warning: Verilog writer has added 1 nets to module mem_ext using SYNOPSYS_UNCONNECTED_ as prefix. Please use the change_names command to make the correct changes before invoking the verilog writer. (VO-11)+ H$ Q1 ~4 U) I; x: j5 C
4 Z" }1 ~8 H( U: k! x8 z/ }4 z! H/ N$ N這是代表我的code哪裡有問題呢作者: cmyang 時間: 2008-4-2 11:23 AM
看起來mem_ext這module是已被synthesis後的verilog netlist, 會顯示Unconnect可能有input or output floating,8 Y1 J; f( _9 U, O/ A) i; d
若是input floating要查看是否有斷線或是沒設定initial value, output floating就沒關係作者: 小人發 時間: 2008-4-9 07:56 PM
原來是floating的問題) q% S5 a& T2 p3 p" d+ H$ L
了解了8 A$ R2 S. k0 K0 I$ q
感謝你的解答 1 `4 b' j7 O3 _; r0 N
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另外還有一個問題 也是在DV階段跑出來的warning 如下:) e% M y3 @9 ~' n% Y. ^: i
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design_vision-xg-t> write_sdf -version 1.0 dpwm2.sdf 4 _* { {" V8 \& m1 S5 nInformation: Annotated 'cell' delays are assumed to include load delay. (UID-282)2 [, T; o- ?4 w3 I' `9 S
Information: Writing timing information to file '/export/home/stevetu/batman/dpwm2/dpwm2.sdf'. (WT-3)% z4 J9 [4 E& \% z+ D0 o
Warning: Disabling timing arc between pins 'CDN' and 'Q' on cell 'mp_dpwm1/DFF_reg[102]' $ ?! c C5 P+ }5 u' C% z; t: N to break a timing loop. (OPT-314) ( u$ ?5 K$ ]1 n4 ?4 P8 z* MWarning: Disabling timing arc between pins 'CDN' and 'Q' on cell 'mp_dpwm1/DFF_reg[10]'+ m, K; o& y) O+ [+ v
to break a timing loop. (OPT-314)2 x7 l8 D8 V7 x0 v4 l. o
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