標題: What Verification IP do you plan to use MOST on your current design? [打印本頁] 作者: atitizz 時間: 2013-9-5 03:34 PM 標題: What Verification IP do you plan to use MOST on your current design? Please indicate whether the IP exists internally or is purchased from 3rd-party... 5 R4 M2 T( B! n( r: d+ {0 D+ u1 R; ^4 p3 [
Other (please specify):作者: ranica 時間: 2013-11-11 10:53 AM
ASIC工程师 + F5 n8 I& d/ ^# a5 U) a" M公 司:High-technical IC supplie with commercial FPGA intellectual property 8 v: k6 H/ \( n工作地点:北京, J2 _% \; ~: [( h. N
! ?( G4 B2 S; l* r职位描述9 S; C' o/ h! T
1.微电子相关专业硕士学历, 3+年ASIC前端工作经验(不含在校、实习); : a8 H! m6 t% u/ i& Y, ]
2.熟悉并参与过ARM或MIPS等常用SOC架构的设计、应用,对SOC架构及常用外设的工作原理有深入理解。 " ]6 {# m. g4 q0 [: x7 `/ m) z3.精通verilog语言,能够独立完成verilog module design,拥有良好编程习惯codingstyle。 , v e$ R8 l1 P% [$ q6 m4 M' W
4.能够独立完成单元级仿真,在系统仿真中承担部分工作。 2 u1 ]4 b! f5 j) j5.至少1次成功流片经验。 ; r8 P5 H E5 o4 d/ F
6.对synthesis、sta、dft等有一定了解。 # J+ s3 F/ \. m2 A* {0 z7.良好的团队合作精神作者: ranica 時間: 2013-11-11 10:53 AM
职位要求 1 l& D+ w1 M% t5 K# E% X* y, r( {全部或部分满足以下条件者优先考虑: 6 P. t6 s v! u, }* e9 y: o- D1.有在大型asic公司工作经验,深入理解其企业文化。 $ k, f1 y3 T/ y) e# j
2.熟悉验证方法学;熟练使用SystemVerilog等专用语言进行验证平台的搭建和维护。对Testcase规划、覆盖率分析、门级仿真、ATE testpattern产生等有实践经验和深入理解。 ) t7 L h9 _/ d4 x3. 丰富的fpga emulation经验,能熟练进行板级debug,编写调试简单driver。 ; P: b h4 r) Z, p2 O/ i6 N" a+ W4 s
4.对芯片系统架构有一定理解,能进行子系统级别的独立规划设计。对以下知识中的至少2种有实际经验: 9 L; w9 g! q& N& oARM/MIPS/8051 CPU及其架构, 0 I5 X* C$ I0 y+ ]3 Q' fAMBA(AXI/AHB/APB) 总线、OCP, ( v4 f/ p! M# A. D! K- A4 DUSB(3.0/2.0/1.1, $ P7 D0 {! i6 ]* ?9 s
NAND/Nor Flash/S-flash controller : e: i V3 l4 `7 p% eDDR(2.0/3.0)controller/PHY & T! J. H6 S0 S& tlow power design, - W6 n8 w0 c, q# V9 `9 Schip level clock/reset generation and control, " d, a7 G. |6 ?/ u4 c0 OSD card controller, SATA,sim card 0 d$ |0 c) J8 U' Nsoc基本外设 (SPI/ GPIO/timer/WDT/I2S(SSI)/I2C/UART), ' P# V& q6 E& R/ P+ T
Ethernet, 7 |9 s! L2 T! K" q/ u) QJTAG, etc.作者: ranica 時間: 2014-2-11 02:52 PM
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公 司:A famous IC company ) E) m# J7 _) G% B4 |) U工作地点:深圳 ' S& \/ U# {, ^9 P3 l8 X3 V8 {! a' ^5 U, \3 D% l( F3 v
Key Responsibilities * X! u/ t2 n, U# p0 E 4 m, j# U I W2 o: ?7 ] Y IScope prospected and qualified IP opportunities develop strategies and processes to increase IP licensing and design wins opportunities. : G( O8 T; C5 h! U* k
# q. g6 E0 j4 q: I: U! GRemove technical obstacles and provide a path to increase IP licensing and design wins opportunities. / e# x6 U: e/ T" \* Y0 ^
2 V! R* q0 O9 Z1 ^. W! O/ z9 lPresent and demonstrate technical details of xx products to customers. ; H6 K0 d$ p7 `7 ?6 F- M# Y / w+ o2 r5 R/ CProvide technical support in pre-sales opportunities as well as ownership of customer support process. . }# ?, W% y- f" N! x, C i1 |2 e& P9 m
Provide appropriate product recommendations to meet customer requirements . C5 ?& S8 M& ~; G8 n9 s/ D
, R" n% T5 D8 o9 h8 I' `" _Provide system design expertise and first pass architectural planning for products in early design stages作者: ranica 時間: 2014-2-11 02:52 PM
职位要求0 p' V, W P8 o7 ~3 s
Education & Qualifications ( P6 j/ ^$ E$ d
Qualified candidates will have a good university degree in Electronic Engineering, Computer Engineering or Computer Science. Master degree is a plus. * e( i+ T1 Z, a- | , h( S- X" C/ q" K5 @# k0 X2 TProfessional Skills and Personal Requirements % N" Y3 N7 Z9 o
Excellent communication skills ; G5 A- q0 _8 x: G+ p, K( kHighly self-motivated with the ability to effectively work alone as well as in a team ) ?& D; J3 S3 l5 i s' Q
Must have the desire and ability to solve problems quickly. , C2 O1 [3 v3 J+ L
Demonstrate a positive attitude and respect for all members of the team ( ]* [. q# e+ `5 e" x# p* zBe motivated to continuously develop skills and accept a variety of responsibilities as part of contributing to the team’s success! F# J) L+ C7 c+ Q' J
Willing to travel both domestically and internationally, approximately 30% of time, spending significant periods of time on customer sites and for learning trips. 9 V& ?3 ?" v5 p+ YGood spoken and written English $ J) B. ~3 H" M) x( _Customer related experience is a plus, but 10+ R&D experience is must-have. 5 ~; c" q/ U k/ s. A/ c " ~) S3 m. u) o! r5 l) q* J8 O ]Essential Technical requirements . z+ G6 [, }/ d9 A1 J9 i$ {
7+ years experience in IC hardware design. xx SoC tape out experience is a plus. 6 F$ L5 g# N6 }9 N7 F+ n- v
Working knowledge of ASIC Implementation (Verilog, Synthesis, P&R, and Timing analysis), including relevant EDA tools and methodologies.8 S3 a* X; R- ?6 N, R
Experience at the system architect level with intimate knowledge of bandwidth analysis, low power design, performance optimization etc & m1 S/ q/ ~% @3 K- ^# R" ^- M
GPU experience is a plus. 3 ?3 s6 b, A: @Consumer application experience is a plus作者: innoing123 時間: 2014-2-27 01:35 PM
Brocade在其數百萬兆位元(Terabit)核心路由器中整合了Altera的120G和150G Interlaken IP 6 J& i* H$ T# l+ R b採用含有Interlaken IP的Stratix V FPGA,Brocade線路模組能夠靈活的根據雲優化網絡進行擴展' v) e$ P3 K+ b9 n5 r
& k* G5 z$ P+ k7 R* ~3 _, EBrocade公司ASIC和硬體工程副總裁Majid Afshar評論表示:「Altera為我們提供的這一種Interlaken IP設計能夠非常靈活的進行配置,而且非常可靠,滿足了我們各種線路模組配置的寬頻效率需求。這種獨特的配置設計結合我們的服務成本模型基本結構,讓我們的企業和服務提供者客戶獲益匪淺,他們對預算要求非常嚴格,而且需要的服務比較特殊。Altera的Interlaken IP頻寬可以擴展,具有很高的資料效率,滿足了客戶對大資料的需求,同時也滿足了需要透過網路高效率傳輸資料的其他應用需求。」6 k d! W' x. H4 V* ^: Y
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Altera採用Stratix V FPGA架構的Interlaken解決方案支援速率高達100 Gbps以上的晶片至晶片資料封包傳送,協助OEM傳送每天產生的近2.5艾位元組(exabytes)資料。Interlaken IP是完全整合解決方案,包括了MAC、PCS和PMA層。作者: innoing123 時間: 2014-2-27 01:36 PM
Brocade採用Stratix V FPGA架構的百萬兆位元路由器解決方案為企業決策層提供了:. D! w- w+ X& d1 c1 H2 T, c* {
% ~1 N7 x$ a0 Z9 w' M$ [• 為軟體定義網路提供高密度100吉位元乙太網路(GbE)、40 GbE和10 GbE路由以及真混合埠模式的OpenFlow支援,靈活的流量控制以回應動態資料流量碼型,滿足了業務需求。/ Y0 B. F& F, B3 W
• 可靈活擴展的IPv4/IPv6路由和高階MPLS功能,提供線速100 GbE和10 GbE密度——非常適合網際網路骨幹網路和服務提供者核心網路應用。 * O2 I* ~! J4 S3 U# z' n# ?• 高性能價格比結構,讓管理人員能夠靈活的購買服務和頻寬,進而提高其競爭力。5 P6 v! j r2 l' j: ?8 i: b
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Altera通訊業務部資深總監Dan Mansur評論表示:「Brocade透過其創新路由器不斷簡化並擴展網路基礎設施。我們的FPGA和Interlaken解決方案為Brocade這樣的公司提供的優勢,不僅僅在於滿足了當今資料中心的性能需求,而且其設計方式可以支援未來應用的傳輸量和介面更新要求。」 4 o$ ^- t6 w, N: E 2 i* {0 T/ a- H6 a: D2 iAltera的Interlaken IP核心可以擴展滿足對更大頻寬、更高性能的需求。IP通過了大量的模擬和驗證,能夠可靠的運作在多個內部和客戶平臺上。作者: ranica 時間: 2014-5-14 01:56 PM
IP验证工程师2 N% V5 f0 M- Q$ h# K1 h6 \( m K/ C5 Q
公 司:A famous IC company " C: }4 X7 N7 y" _$ r. _7 f工作地点:苏州 # B% {4 e9 @5 D0 p, T7 K " E4 w* z7 D+ N3 `% m3 a h7 b' Z/ ~( r职位描述: ) B6 D+ s, d3 w" C
1. 负责PowerPC等平台上的软件设计、开发、测试 5 I( ~* S4 A! d* B- u* e2. 配合IC设计人员完成芯片开发验证工作 2 @/ c& [: X- G- |3. 负责相关技术调研,编写相关开发、测试文档 , h9 Z2 d6 M" o" e" e7 O4. 负责芯片及应用方案的市场推广和技术支持工作 6 J5 R% X1 j+ M5 m: L7 \! _( p* C- L( e) V" u- U4 x1 j1 W! a
岗位要求: : o3 ?; P9 q( h8 i% ]- o& N" q1. 计算机、电子类相关专业,本科及以上,三年工作经验; 5 F0 a5 d8 u5 C0 n2.精通C/C++语言,数据结构,丰富的产品应用开发经验; V, C" t! `. K# `9 _& c# }
3. 至少对一种嵌入式CPU(CCORE、PowerPC、ARM、MIPS等)有深入了解和实际产品开发经验,熟悉PowerPC架构者优先; 8 p" n! h- j0 \! _: n4. 熟悉硬件IP,如PCIE、USB、DDR等,有相关IP测试经验; / d. h* V: N& H% T6 m
5. 工作扎实认真,服务意识佳,善于与人沟通,具有团队合作精神、能够承受高强度的工作压力;作者: ranica 時間: 2014-5-21 09:32 AM
IP验证工程师 % X* |9 [5 d% Y) A1 F: v w公 司:A famous IC company ; B* r3 z6 n. y; u0 @7 X$ ~6 ^& @工作地点:苏州 - H" [+ S, x3 u( \- z& A1 e: E4 D, D: K5 w. b
职位描述: 5 |. e" O- w$ I' M, {8 n1. 负责PowerPC等平台上的软件设计、开发、测试 . P0 M% T) a2 B+ ~1 ?+ n2 M$ G
2. 配合IC设计人员完成芯片开发验证工作 4 E* u1 o2 ^* T7 K7 {
3. 负责相关技术调研,编写相关开发、测试文档 ' f: _4 H6 t8 D& c, a2 a! r i4. 负责芯片及应用方案的市场推广和技术支持工作 - x; k v% I( ~! R9 u% A- I 6 [- m3 Y. W$ M- p岗位要求: / z: J3 a' I" K& P
1. 计算机、电子类相关专业,本科及以上,三年工作经验; $ b5 ]: {5 x0 F: O- p; u0 L5 K
2.精通C/C++语言,数据结构,丰富的产品应用开发经验; 8 v- t1 P) j9 K) O: W4 _2 `/ b3. 至少对一种嵌入式CPU(CCORE、PowerPC、ARM、MIPS等)有深入了解和实际产品开发经验,熟悉PowerPC架构者优先; / K$ o: z6 c2 b0 d4. 熟悉硬件IP,如PCIE、USB、DDR等,有相关IP测试经验; ' q% n+ s1 T" b( N' G
5. 工作扎实认真,服务意识佳,善于与人沟通,具有团队合作精神、能够承受高强度的工作压力;作者: ranica 時間: 2014-5-30 11:34 AM
IP验证工程师- [( D- J2 c! V& ]" s
公 司:A famous IC company7 |3 @& \1 \! U. d+ Q0 U
工作地点:苏州 ; M/ n9 p/ a8 \4 r; H , f7 T0 K3 O$ O职位描述: : T, O; i. v, C$ N; f! u$ ~1. 负责PowerPC等平台上的软件设计、开发、测试 / r5 {2 B. f$ a$ n
2. 配合IC设计人员完成芯片开发验证工作 2 ]3 ]5 N' b7 a0 H% ^
3. 负责相关技术调研,编写相关开发、测试文档 + Y- f7 ^* h5 K) Q$ q; Y0 Q; U
4. 负责芯片及应用方案的市场推广和技术支持工作 ) L$ A) M* p9 K( I4 o
' I2 f! q3 m: g- Z1 ?/ t6 B岗位要求: H9 {0 N* L. y( d1. 计算机、电子类相关专业,本科及以上,三年工作经验; ! Y& f, U/ u1 T1 F2.精通C/C++语言,数据结构,丰富的产品应用开发经验; - ~! Z' X9 e9 n# L! ?! q; v3. 至少对一种嵌入式CPU(CCORE、PowerPC、ARM、MIPS等)有深入了解和实际产品开发经验,熟悉PowerPC架构者优先; 3 i0 s \. r+ i# W" k- n
4. 熟悉硬件IP,如PCIE、USB、DDR等,有相关IP测试经验; ! N1 v9 W# ?: B/ x; q! g0 r( S5. 工作扎实认真,服务意识佳,善于与人沟通,具有团队合作精神、能够承受高强度的工作压力;作者: ranica 時間: 2014-7-16 08:19 AM
ASIC Verification Engineer (WMAC) / @' i* a! l% `- H! l% z7 X5 m. `5 [1 d1 n
公 司:A famous IC company 9 z! t2 a1 k+ v* }1 l: Y工作地点:上海 # S+ D# m& Z1 r" S' A ( K* D, f, c1 w. K i( d' @The Role: 1 t& ?0 ]' e6 j$ P7 C0 i ASIC design and verification % i6 v, i9 d" Z: z a5 Q2 z
Work closely with the California teams * f+ ~: t4 m( u- T9 C) P) K
Support chip tape out and bring up ; h. c; k# l1 E$ C* K* A. X/ I1 K2 x2 a% y3 \
Requirement: 8 e- ?" \3 N/ x/ E7 f1 z
8-10 yrs. experience 4 w& @4 t3 e8 ]% @( K( Q. q$ z Knowledge of Verilog / System Verilog & Perl 3 C( C9 a0 g( o2 M2 T! { Has worked on complex project; experience with 802.11 is preferable 4 H0 S& i( h+ Z Can work independently - want him to take over MVE * X$ O7 l$ n) ^ Experience in Networking SOC, Ethernet MAC or any other MAC layer protocol experience is plus作者: ritaliu0604 時間: 2014-7-17 09:32 AM
ASIC Verification Engineer (WMAC)9 s8 A6 a) s4 a- h, V- @9 q; B
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公 司:A famous IC company+ E- y/ f8 z0 q# T) a: c
工作地点:上海 6 T- X5 h2 K0 A9 o1 f % ?9 Z$ T* u% T* B8 h) vThe Role: * ~, D2 V8 }/ a) k+ P
ASIC design and verification ) x c8 {1 D3 `2 w4 j6 i! Y6 r
Work closely with the California teams ( j- r) q+ a9 c! v" Y
Support chip tape out and bring up * Q+ s5 Z7 X$ o7 }( R) R! f w 5 e* R5 f% h5 @3 bRequirement: : C7 p% N$ z" x8 b- ^ 8-10 yrs. experience 0 ?: v+ O4 P& C$ c0 x Knowledge of Verilog / System Verilog & Perl . k& p5 S2 G) v$ H Has worked on complex project; experience with 802.11 is preferable ( b. f! R9 f, h Can work independently - want him to take over MVE $ \3 j. z! r+ Q
Experience in Networking SOC, Ethernet MAC or any other MAC layer protocol experience is plus作者: sophiew 時間: 2014-7-25 10:56 AM
Job Title igital verification Engineer , B5 h* a8 d1 b7 N$ j: ]* BJob Category :Semiconductor8 c" m+ E1 I R# ?* z* ~3 V
Location : Singapore. {: ?+ ~' l: f/ b
Job Type : Permanent / ^/ k' a( d( @5 oJob Description:( ^! ^- ~( b. L& f" |8 v, Z/ B
Looking for SoC Verification Engineers Experienced in System Verilog Tools; P! Z! }: H2 s- d$ |9 t1 T; |
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Responsibilities: # [; `7 S) G: ^ sConstrained-Random Verification using SystemVerilog.9 ?1 @3 _* _* Y
Develop verification environment for DUT,Write and debug tests for DUT using SystemVerilog, Perl, and C. 1 l5 f, T: Z- F2 _4 v% d4 gDevelop Bus Functional Model(BFM) or using Verification IP(VIP) for tests- M1 |! A! ~) \! l" `/ u
Developing and reviewing test plans3 J4 `+ H, r1 J4 W9 h
Write coverage monitors to evaluate the coverage of the DUT. ( V7 C1 ?' ^$ E$ ~3 n* EFormal verification using SystemVerilog Assertion to verify SOC or IP is plus/ k# r, O5 |: d) g
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Requirements: " ], [0 I7 _! e$ \/ q! d>4+ ethernet switch background 6 J4 s; w. \9 E7 `' T8 oAt least 3-year+ experience on digital design and verification4 x: e- t- p; K& I
Experience on SystemVerilog/VMM/OVM/UVM (UVM is plus)4 i' i" ~" L/ e6 X% Q
Familiarity with transaction-level verification at higher-level of abstractions is plus.1 y. \" s0 h2 G% ]0 y
Experiences in developing measurable verification plan. 2 w! r. g8 D3 R; U" rProficiency in UNIX scripting languages and utilities such as csh, sed, awk, and Perl.