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請教 Synplify "reduced to a combinational gate by constant propagation"
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作者:
kuhwakimo
時間:
2011-3-24 03:35 PM
標題:
請教 Synplify "reduced to a combinational gate by constant propagation"
請教 Synplify Pro9.6.1 Warning Message
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Sequential instance sLateCol_p has been Sequential instance sLateCol_p has been reduced to a combinational gate by constant propagation
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請教個問題，下面是Synplify 9.6.1 出現的Warning message ,
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請問這是什麼意思 ??
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我由字面上的理解得到的猜測是，將一個本應該是FIFO Sequential circuit ,合成為 Multiplier Combinational circuit
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為什麼 ld_tdr_cur_f 會被合成為Combinational, 但是 dly_tdr_wrn 卻不會 ??
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誰有相關的經驗嗎 ??
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@W: MO129 :"\projects\dm8606c\rtl\tff256x64.v":932:3:932:8|
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Sequential instance ld_tdr_cur_f has been reduced to a combinational gate by constant propagation
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reg ld_tdr_cur_f;
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reg dly_tdr_wrn;
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//------------------------
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// delay 1 clk
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//------------------------
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always@(posedge sclk)
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begin
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ld_tdr_cur_f <=#td1 ld_tdr_cur;
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dly_tdr_wrn <=#td1 tdr_wrn;
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end
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// 下面是 ld_tdr_cur_f , dly_tdr_wrn 的loading
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always @(posedge sclk)
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if (ld_madr & !wr_nxt_tdr)
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wr_save_1st <= #td1 wr_counter;
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else if (ld_tdr_cur_f)
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wr_save_1st <= #td1 wr_save_2nd;
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always @(posedge sclk or negedge rstn)
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if (!rstn)
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rst_ff_pt <= #td1 1'b0;
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else
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rst_ff_pt <= #td1 (!tdr_wrn & dly_tdr_wrn & tdr_empty);
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always @(posedge sclk or negedge rstn)
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if (!rstn)
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rst_ffpt_sync <= #td1 1'b0;
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else if (!tdr_wrn & dly_tdr_wrn & tdr_empty)
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rst_ffpt_sync <= #td1 1'b1;
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else if (rst_ffpt_clr2)
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rst_ffpt_sync <= #td1 1'b0;
作者:
yadog
時間:
2011-5-5 10:28 AM
不清楚要实现什么功能
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但是在写法上有些问题
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if (ld_madr !wr_nxt_tdr) 这句是否笔误？ld_madr ，wr_nxt_tdr是两个信号把？
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另外if else if写法均不完备，建议将else项完备
作者:
kuhwakimo
時間:
2011-5-16 06:56 PM
是貼上去的時候出現亂碼,更正如下
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//------------------------
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// save start pointer for 1st pkt
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//------------------------
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always @(posedge sclk)
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if (ld_madr & !wr_nxt_tdr)
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wr_save_1st <= #td1 wr_counter;
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else if (ld_tdr_cur_f)
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wr_save_1st <= #td1 wr_save_2nd;
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