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[關於] [jianping ]如何用verilog將變數前後補上幾個位元
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作者:
tommywgt
時間:
2009-11-5 05:40 PM
標題:
[關於] [jianping ]如何用verilog將變數前後補上幾個位元
本帖最後由 tommywgt 於 2009-11-5 05:41 PM 編輯
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因為無法回覆, 所以開新文回答....
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ABT={2'b00, DATA, 4'b0000};
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Verilog 常用的operator
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– Binary bit-wise operators: ~, &, |, ^, ~^, ^~
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– Unary reduction operators: &, ~&, |, ~|, ^, ~^, ^~
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– Logical operators: !, &&, ||
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– 2’s complement operators: +, -, *, /, %
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– Relational operators: >, <, >=, <=, ==, !=, ===, !==
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– Logical shift operators: >>, <<
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– Conditional operators: ? :
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– Duplication operators: {n{ <exp> <,<exp>> *}}
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– Concatenation operators: {}
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給你參考一下
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