圖一 全球MPEG-4/H.264 IC出貨與營收預測7 k- a& q8 W4 R/ l1 B* ^% O7 ^( h3 D
" k" `; Y/ |, d1 u圖二 IPTV應用架構圖* ~3 I" i- m/ P7 v( V5 [
) m9 g5 J5 t7 I+ A, C4 e+ g; _圖三 Set-top Box全球出貨預測& X+ p. b7 Q" q* t+ v
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圖四 2006~2010年全球視訊監控市場預測
圖五 2006~2010年數位相框銷售量與成長率預測% e6 q) t) f) @; H3 H
●Decoder Elementary Stream compatible with the ISO / IEC 14496-10 specification2 w2 U9 c1 z9 m8 ^4 ?( P3 {Block Diagram
●Supports main Profile Levels L1 to L3 and thus baseline H.264. [+ h# E+ K+ @6 h% L4 v: P$ h
●Intra Prediction3 C: `( |4 ?/ l, A) i0 e& j* G# E
●16x16, 16x8, 8x16, 8x8, 4x8, 8x4, 4x4-MV(Motion Vector), Unrestricted MV
●I-Slice / P-Slice prediction type
●Scalable resolution up to XGA(Multiple of 16 in height and width)* P- h+ C; x. A Z5 {1 N% q
●Frame Rate up to 352(288 @ 30 fps, 640(480 @ 30 fps, depends on working clock rate9 [- c2 i4 N5 @7 ~/ x" R) l3 L
●Support CCIR-656 YCbCr 4:2:0 and 4:2:2 raster video input/output
●Variable Length Decoding (CAVLC/CABAC)/ A J3 Y% U _4 X+ H) o$ a& b* J
●FPGA verification
●Compatible with the ITU-T H.264 baseline profile* s" N$ p7 y; t X0 p1 E3 qBlock Diagram* L! L6 W6 |& t3 I$ Q; Z! I# S4 M- U
●Fully 4’4 (9 modes) and 16’16 (4 modes) Intra predictions
●Hierarchy Inter mode prediction
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16 x16、16x8 、 8x16、 8x8 block modes+ d2 O! t3 @& Q9 a# N( t6 N
2.
8x 8、8x4 、 4x8、 4x4 sub-block modes
I-VOP / P-VOP prediction type7 U: m' v2 _& _& p
●Free format resolution from QCIF to D1 or above (176’144 to above 720x480)' |7 r4 c1 L" p8 A- U
●Frame Rate up to 30 fps (352’288 to 720’480, depends on working clock rate)
●Support CCIR-656 YCbCr 4:2:0 and 4:2:2 raster video input/output
●Motion Estimation search range:-16 ~ +15 pixels down to quarter pixel
●CAVLC support& A& o. }$ T2 Y5 X- A* W' G/ f
●In-loop deblocking filter (easy to be online configured on and off)5 I6 \ }# D0 l
●AMBA 2.0 bus interface2 q" h" w$ {+ l1 _* I
●Optional constant bit rate output (control by host processor)
●Driver for encoder configuration and application sample codes. |' }' L1 g' {; P! ], x
●FPGA verified and Silicon proven support6 c6 @ N" K% \1 o7 T$ q( J
●AHB bus at 133 MHZ for TSMC 0.18um Technology
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●RTL source code (Verilog), Q% ?+ D* E" f0 m8 A, c9 V( SCompetitiveness1 o" Y% L; H. S. n* j" h
●Testbench (self checking)
●Simulation script& d+ P' @& E2 j1 P2 W$ v
●Synthesis script1 T `+ K4 \1 x5 K7 O
●Documentation for training course
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●High compression efficiency compared with the standard reference software (JM)4 @( ~/ D4 Y7 q) C1 v: L, @% {Applications
●Low power consumption
●Low gate count for small die size$ b4 a2 v B: } R, f
●Easy to integrate with SOC platform with standard interfaces (AMBA, SDRAM or SRAM)
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●Surveillance video capturing" `+ R4 g1 F2 T. N9 o
●IP video phone/conferencing g+ a* n/ }: U, H2 s7 u* }
●Digital Camera / Digital Camcorder3 E7 R6 R: u* j+ t6 n, E1 `' j0 ?
●IP / Web Camera
●Personal Video Recorder
●Streaming Processors
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