標題: A multi-level approach to low-power IC design [打印本頁] 作者: masonchung 時間: 2007-1-13 10:39 PM 標題: A multi-level approach to low-power IC design The concept of power-efficient design is certainly not new. Low-power design techniques have been employed for more than 25 years, particularly in the areas of watch circuits and calculators. What is new, however, is the requirement of both very high performance and low power at the same time. In some cases these requirements are motivated simply by the need to extend battery life, while in others they are driven by the need for thermal management. 1 {% F+ s' s; H+ C* H2 {
The need has not gone unnoticed. Low-power IC design has become an especially vibrant area of research and development, resulting in advances in low-power fabrication processes and circuit techniques, dynamically programmable power supplies, and power efficient microprocessors. A new generation of computer-aided design tools developed especially for power efficient design is now available to help engineers optimize power at most stages of the circuit-development process. ' D# f4 L! T T Y # l" n& T4 B2 {8 X7 r- J4 A* U. Dhttp://www.sequencedesign.com/2_solutions/IEEESpectrumFeb1998.pdf" \" m3 G) f, V: \2 l1 J
9 s' _4 E% T }# o* o[ 本帖最後由 masonchung 於 2007-1-22 05:54 PM 編輯 ]作者: jarodz 時間: 2007-12-21 11:14 PM
Synopsys had a "Low Power Methodology Manual - For System-on-Chip Design" ebook on their website.' m( @( B, B2 z0 D6 i
If your company licensed their EDA tools, you will have a legal host-ID to register a count to download this book. + l0 ~5 i7 N: {: B) P) P3 z $ E$ \5 ?+ C6 X* qSincerely,' W9 c: S* N# m- ] x
Jarod