`# {$ |. S$ B3 ?$ q' N在開發軟體內容豐富的電子裝置時(特別是針對行動及消費性電子產品),設計人員不但需要將日益多樣的軟體內容納入設計考量,還必須面對軟體開發以及軟硬體整合的挑戰。為了縮短軟體開發的時間,新思科技SoundWave 音頻次系統的Virtualizer™虛擬原型建造,可協助設計人員在矽晶產出的數月前便能進行音頻軟體與應用軟體的整合。該音頻次系統的HAPS® FPGA原型建造解決方案可達成快速的軟體開發,並為全系統整合及驗證提供可擴展的平台(scalable platform)。 6 k# {, H$ X `' R& X
; W) ]) }, Z7 `) G$ G; t1 B' l新思科技IP及系統行銷副總裁John Koeter表示:「設計人員不斷調整方法以因應日益複雜的SoC設計,IP解決方案也需跟著精進。軟硬體的最佳結合能有效支援設計上對效能、成本、功耗及時程的需求。DesignWare SoundWave音頻次系統提供預先驗證的完整端對端(end-to-end)音頻次系統,協助設計人員大幅縮短概念(concept)到實作(implementation)的時程。」作者: amatom 時間: 2012-6-19 11:27 AM
Imagination Optimizes its IP Capabilities with TSMC on Latest Silicon Process Technologies) u# J K V% p h2 S
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Imagination Technologies, a leading multimedia and communications technologies company, announced its collaboration with TSMC to ensure that licensees of all of Imagination’s IP (intellectual property) cores can optimize speed, area and power consumption on TSMC’s most advanced 28nm and below processes.% x& t5 ^6 c; K) O3 Z; V5 y# A0 R
4 y8 v/ g; K/ o5 [+ ]: X* f% l5 H kBy bringing together engineers from both companies, this collaboration aims to improve power, performance, and area by co-optimising TSMC process technologies and foundation IPs with Imagination’s most advanced IP cores, including its latest PowerVR GPUs. 6 L* ]2 v) x+ |: L7 D \7 C: h5 S' u- a
Imagination, a member of TSMC’s Soft-IP Alliance program, is making this announcement as part of a closer relationship with TSMC. Imagination intends to validate its IP cores through the TSMC Soft-IP Alliance program.作者: amatom 時間: 2012-6-19 11:49 AM
Imagination’s IP core families in this collaboration include:( U+ I2 r3 b' h r4 }$ F8 t. E
, W- f, D9 D+ q$ p- y. j8 C# Y•PowerVR graphics, the de facto standard for mobile, embedded and computing graphics: j( y; R( b& n4 H+ f
•PowerVR video and display, the comprehensive and widely adopted range of multistandard decoder, encoder and enhancement cores for applications from mobile to ultra-HD ; }( \% Q& ]8 L8 a9 C- r•Ensigma communications, the multi-standard programmable communications and connectivity technology for TV, radio, Wi-Fi and Bluetooth; W3 e- U, y2 k1 I5 ^1 ]5 o
•Meta processors, the advanced 32-bit hardware multi-threaded processor architecture that delivers the best in both general purpose and signal processing performance ) G' y' }: c$ j* w) v 1 F7 K3 j) v5 y2 @9 iImagination is one of the world’s leading semiconductor IP suppliers, with cores which can be synthesised for a broad range of silicon processes. As more customers use Imagination’s IP cores to deliver the key high performance processing on their SoCs (System on Chip), Imagination plays a key role in the semiconductor IP segment to deliver the levels of performance demanded by leading edge customers.作者: amatom 時間: 2012-6-19 11:49 AM
Says Tony King-Smith, VP marketing, Imagination: “Many of our licensees rely on TSMC to provide them with leading edge low power, high performance silicon foundry capabilities. This strengthening of our relationship with TSMC reflects our determination to deliver the best possible SoC solutions on the latest silicon processes for our SoC IP licensing partners. We believe this initiative will ensure that Imagination’s licensees to continue to push the boundaries of what is possible for future generations of advanced SoCs.”; M% B) @6 n# K- z9 t) C2 f
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Says Mark Dunn, VP of IMGWorks, Imagination’s SoC implementation group: “The characteristics of the latest processes such as 28HPM and beyond have to be taken increasingly into account when designing future high performance IP-based solutions. As major blocks such as GPUs increasingly dominate the area, power and performance of next generation SoCs, design flows need to be tuned to maintain the optimum balance between maximizing IP portability and achieving the best possible performance. We believe this extensive engineering partnership will greatly benefit all of our IP partners.” # ^2 K5 P8 w, c7 Y1 m) h$ V* R! Q ( V9 X, @) b; c5 N$ _“We are delighted to be working with Imagination to deliver the full benefits of TSMC’s latest and most advanced processes for mobile and embedded applications,” says Suk Lee, Senior Director of Design Infrastructure Marketing Division, TSMC. “By leveraging Imagination’s leadership position in the market, we can help our customers to ship the most highly optimised SoCs.”作者: innoing123 時間: 2013-4-16 03:23 PM 標題: 聯芯採用Hantro視頻IP產品 全球基於Hantro視頻IP的芯片出貨總數已超過10億顆, Y/ `$ K. q5 ^ f5 s
& m4 P) U3 i/ [上海2013年4月16日電 /美通社/ -- 為客戶提供定制化芯片解決方案和半導體 IP 的世界領先的 IC 設計代工公司芯原股份有限公司(芯原)今天宣佈,Hantro G1 視頻多格式解碼器和 Hantro H1 視頻多格式編碼器 IP 成功應用於中國領先的 TD-SCDMA 和 TDD-LTE 通訊技術及解決方案提供商聯芯科技有限公司(聯芯)的一系列高性能應用處理器產品中。Hantro 視頻 IP 助力聯芯的產品實現全高清60幀每秒的視頻編解碼能力,並支持包括 VP8 (WebM,WebRTC)、 H.264、 MVC、 MPEG-2/4、 DivX、 VC-1、 RealVideo 和 AVS 等在內的多種視頻格式。 p4 [7 u0 @. ? z0 H K2 t8 y+ a5 `6 C
「從設計之初我們便與聯芯展開緊密合作。」芯原董事長兼總裁戴偉民博士表示:「隨著移動互聯相關設備對視頻性能的要求日益增加,我們堅信第12代 Hantro 視頻硬件編解碼器是目前這類產品應用的最佳選擇。」 . g8 z& A# ^% ]/ `: \! s' Q; M/ t2 N% Y
Google 正積極向業界推廣名為 WebM 的免費、開放的媒體文件格式。芯原作為 WebM 生態系統的合作夥伴,可向全世界範圍內的半導體廠商商業授權 Hantro G1 多格式解碼器和 Hantro H1 多格式編碼器 IP,並有權修改 Hantro 視頻 IP 以加強內核架構和增加新功能等。目前,Hantro 視頻 IP 已獲得全球範圍內70多家半導體廠商的採用,基於該 IP 的芯片出貨總量已經超過10億顆。 9 N5 x+ Z4 R9 A5 ^7 e0 g; j2 V6 Y1 E
「Hantro 視頻 IP 使得我們的產品在具備出色的視頻性能的同時,還兼顧了功率和成本效益。我們感謝芯原在合作中所展示出的優秀的專業技術實力和客戶支持能力。」聯芯副總裁劉積堂表示,「我們的產品可支持包括 VP8 在內的多種視頻格式,並已被許多知名的智能手機和平板電腦品牌廠商所採用。」作者: mister_liu 時間: 2013-5-22 02:27 PM
Principal Product Engineer-----DDR IP 5 X V$ s; l) f0 J0 k, ^$ ?% z公 司:NO.73-One world top EDA company 4 [7 h) K3 A! V' ~工作地点:上海 9 L6 q* a- R+ m6 S/ H. p- c : y: T1 ]% l* [7 L$ @9 FPosition Description: 9 m3 Y( \: v+ z5 {* c- @. \Our client is looking for an individual to work in design IP team. The group provides configurable DDR memory controller and PHY IP for ASICs. The job will be mainly focused on providing post technical support to customers; however there will be a variety of other engineering tasks that will allow the candidate to expand skills and responsibilities. ( g& w9 F) Y, z1 t$ M' ?% k& f6 B! O. g$ c
Provide technical support to customers for integration of IP into ASICs including: 1 H% M7 B- l: H4 D- Debugging of customers’ simulation or silicon issues. 4 B9 b7 P1 C7 {7 `; f+ S
- Reviewing of customers’ design integration of our IPs.; F# S; E+ H! W1 M) P( f" T! B
- Reviewing static timing reports to assist with customers’ timing closure. ( n4 G+ t; P" ]9 x. r, {' A7 q
- Answering technical questions about IP operation. % b0 s j1 H x5 @- Train field engineers in IP operation.# K3 j0 x. w8 X+ t3 D2 W8 K
- Interface with the R&D Team to bridge product improvements and resolve customer issues. # L% \* S+ a% R1 r4 }5 Y+ b ( \! i! }9 L3 ?/ R6 t. R4 uPosition Requirements: / V9 A2 E# Z" |0 |
- Excellent oral and written communication R m5 t& z1 [/ ?
- Good English communication skill Y4 w6 R( l! a, S2 u P
- BS 8+ years of prior work-experience or MS 6+ years of prior work-experience 1 A# j) U2 c9 a5 L' w7 M) ~- All front-end skills – RTL design & verification in Verilog, synthesis, static-timing analysis, DFT 3 | i9 w$ Y8 U& g5 [- Back-end skills – place & route, physical verification, timing closure & {6 Q4 f _) Y3 E- Time management skills sufficient to balance multiple high-priority projects.! q* D5 G; U$ p: U* l! q; O9 D4 X. ?, Z
- Willingness to learn new skills and perform tasks that often go outside area of current expertise. : Z9 z( z: t9 a8 o; D, u4 k5 A" J: ~$ r' k. d9 |' o/ T6 k
Additional Desirable Qualifications: 5 S8 i% [5 v) z. j$ S p- Experience with Static Timing scripts and report analysis4 k0 h' b A1 m, c# C- |$ z
- Familiarity with DDR memory operation, system applications, AXI, OCP, AHB7 E: l! v* Y! p8 @' F" V
- Familiarity with Frame maker $ W, [! h& R/ m0 ]' e+ |: g- Scripting – in Perl, TCL, etc..作者: tk02376 時間: 2013-5-23 04:23 PM 標題: Imagination:第三方IP成為推動半導體業者發展的重要力量 [attach]18381[/attach] , T9 e8 X; t+ T' CImagination可為SoC所有重要功能模塊提供IP解決方案 ( P w/ ]8 i/ M9 w( f5 }: k! T- L0 {6 A" s# e- G, `+ f: o
(台北訊) 隨著半導體製程進展到28/20奈米世代,製造與設計能力間的落差也越來越大。晶片設計人員為了能在最短時間內將更多樣的功能整合到系統單晶片(SoC)中,採用第三方業者提供的矽智財(SIP),而非自行開發,已逐漸成為一種趨勢。透過運用高品質、完整的第三方IP解決方案,晶片設計人員能將資源專注於開發具差異化特性的產品,包括連結各種IP模塊的設計方式。因此,這已使得SIP市場近年來成長的快速。 0 {; r) u. W+ Q9 [$ w* _ z( I6 p4 R
根據研究機構Markets and Markets發佈的數據,全球SIP市場營收預計將從2012年的25億美元到2017年成長到57億美元,年複合成長率(CAGR)達14.5%。特別是,在行動裝置、各類消費性電子創新設計帶動下,處理器IP市場的漲勢最高,達21.2%,表現優於整體市場。作者: tk02376 時間: 2013-5-23 04:23 PM
而在處理器IP中,GPU(繪圖處理器) IP由於具備平行處理特性,有更佳的可擴充性,已成為近來推動行動SoC效能提升的重要力量。此外,結合CPU與GPU的異質運算架構,也將能夠進一步提升效能與降低功率,將能為新一代SoC設計開啟全新機會。 - {# E- v+ v H. q) l4 e
) m, g6 L5 q" }* t& z( Q- l" z4 A: H該公司表示,更佳的使用者繪圖介面(GUI)需要更高的畫素處理能力,不僅行動裝置,汽車和其他產品也朝此趨勢發展,像是數位化儀錶板、資通訊娛樂系統,以及後座娛樂裝置、多螢幕顯示等,都些是靠GPU來實現的。 ( s6 w$ Z; ?! Y& V: | ( \, t; D' C0 c0 dImagination強調,有效運用CPU、GPU和通訊處理器等不同的處理器不僅已成為推動各類新式應用的重要力量,對於設計方法、製程技術也扮演了重要角色。同時,異質運算將為SoC帶來重大變革,為使用者介面、遊戲、多媒體等終端應用激發出更多創新功能。作者: tk02376 時間: 2013-5-23 04:23 PM
Imagination可提供完整的SoC IP解決方案。Imagination的廣泛IP組合包括市場領先的PoweVR繪圖、視訊、顯示IP、MIPS CPU IP、創新的Ensigma通訊IP,以及HelloSoft V.VolP與VoLTEIP、和Flow雲端連接性IP解決方案。這些技術能為客戶提供獨特的差異特性,以及功能最強、最具成本效益的解決方案。 + I2 k% c1 a. Y9 F. W# k- u
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此外,Imagination在今年初併購MIPS後,強化了其既有的CPU IP產品組合。Imagination原本就已積極開發CPU技術,納入MIPS後,將更能加速此計畫的實現。這項併購行動有助於公司提供完整的領先IP解決方案,以滿足新一代消費裝置的設計需求。 ; P0 ]- O' h- n1 v2 J
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看好台灣市場的發展潛力,Imagination自去年(2012年)首度在新竹舉行技術論壇獲得熱烈迴響後,今年(2013年)更將擴大舉行,預計於6月26日和6月28日兩天分別在新竹、台北兩地進行IMAGINATION高峰論壇。這是Imagination在併購MIPS後首度舉辦的技術論壇,開發人員將能全方位瞭解Imagination與MIPS結合後的完整技術方案以及最新的SoC設計趨勢,並特別邀請到Imagination的重要生態夥伴成員發表專題演講。請千萬不要錯過了我們為本地開發人員精心安排的一整天精彩活動! " [0 q/ P9 a) E8 \% w% f$ w* c& _* n
【活動資訊】 0 d# b* l: U! X活動日期、地點: 2 c5 |# T+ v2 D( s2 Zl 新竹場6月26日新竹喜來登大飯店(新竹縣竹北市光明六路東1段265號)- K2 p! a3 z2 E9 O* f3 s. L
l 台北場6月28日台北六福皇宮(台北市南京東路三段133號)作者: ranica 時間: 2013-6-13 10:57 AM
Principal Product Engineer-----DDR IP . Y2 R. F L# X9 n: ]# K公 司:NO.73-One world top EDA company: N2 t' C" \* E' V. w; Y
工作地点:上海 1 z/ X) G4 D: W& U4 i' H$ S, M # u/ w: C; F: B" V5 W/ s6 Z$ q1 APosition Description: * O6 d; ~8 h8 C1 V0 g
Our client is looking for an individual to work in design IP team. The group provides configurable DDR memory controller and PHY IP for ASICs. The job will be mainly focused on providing post technical support to customers; however there will be a variety of other engineering tasks that will allow the candidate to expand skills and responsibilities. % ]# z4 w# M0 j1 ^5 y* O" ?
5 f9 E G& O9 L' z* K, p! ?: FProvide technical support to customers for integration of IP into ASICs including: , c" X* q: v. K
- Debugging of customers’ simulation or silicon issues. # B+ Y' c: {& Z& b
- Reviewing of customers’ design integration of our IPs. 6 M# _$ A3 ^. [+ \. C+ S4 i7 k- Reviewing static timing reports to assist with customers’ timing closure. ' D: |. X, R" `% |* a0 V. b& i
- Answering technical questions about IP operation. 9 N! h9 h+ U; ]2 z0 F. \3 U8 q- Train field engineers in IP operation. : ~! H5 Y6 E: L) ^! V# O' a+ K8 A- Interface with the R&D Team to bridge product improvements and resolve customer issues. / B7 q$ j: d* t' F- N/ y3 L+ j( F$ ?- n
Position Requirements: ; X6 t7 k+ F- _/ @: R+ n; C- Excellent oral and written communication ' i8 y% B1 k+ T/ }
- Good English communication skill , @: t7 { g v( d: A! |# b- BS 8+ years of prior work-experience or MS 6+ years of prior work-experience ( k% W8 s5 c* K# F3 k( Z- All front-end skills – RTL design & verification in Verilog, synthesis, static-timing analysis, DFT 8 Y; @" L1 R2 H0 Z1 }- Back-end skills – place & route, physical verification, timing closure 5 ^% z& R6 Y! z9 c
- Time management skills sufficient to balance multiple high-priority projects. % {6 f z7 h8 k z
- Willingness to learn new skills and perform tasks that often go outside area of current expertise. ! y! P( u0 V5 T E/ h
' F" ^) w) p8 V$ x. ^Additional Desirable Qualifications: ) g$ T r) U5 m `- Experience with Static Timing scripts and report analysis / U ~% F- ]) i
- Familiarity with DDR memory operation, system applications, AXI, OCP, AHB ! h$ D% D6 W( m D; h1 W- Familiarity with Frame maker ; j8 N {* ?. N6 S
- Scripting – in Perl, TCL, etc..作者: sophiew 時間: 2013-7-2 09:44 AM 標題: 芯原發佈支持HEVC和VP9的Hantro G2視頻解碼IP 全球首款同時支持HEVC和VP9視頻格式的半導體IP 2 U- L3 \3 T2 X3 N% q2 a, j) x 5 e; W, N6 _' [. E; w7 _5 E上海2013年7月1日電 /美通社/ -- 為客戶提供定制化芯片解決方案和半導體IP的世界領先的IC設計代工公司芯原股份有限公司(芯原)今天宣佈推出Hantro G2多格式視頻解碼IP,支持高效率視頻編碼(High Efficiency Video Coding,簡稱HEVC或H.265)標準下的超高清4K視頻解碼,以及 WebM項目下即將推出的VP9網絡視頻格式。此外,Hantro G2 IP還支持包括H.264、VP8、MPEG-4、VC-1、AVS(即將支持AVS+)、MPEG-2、DivX、Sorenson Spark和VP6在內的其他多種視頻格式。 A/ Q# L: Q( c: h& A, B- ?
7 u" l/ s1 S( L. L作為可擴展的IP解決方案,Hantro G2可根據客戶對產品性能的需求來優化硅片面積,並支持從4K@60 fps播放速率的高端應用、到1080p高清播放的中端應用,再到標清播放的低端應用,從而廣泛適用於從超高清電視產品到低端功能手機的多樣化市場。 Hantro G2是業內首款在一百萬邏輯門以內支持4K@60 fps的單芯片架構IP。業界領先的Hantro視頻半導體IP已經被全球超過75家半導體廠商應用於超過10億片芯片之中,而Hantro G2是Hantro視頻IP的第十三代產品。作者: sophiew 時間: 2013-7-2 09:44 AM
VP9是由谷歌(Google)發起的WebM項目所開發的下一代開放視頻編解碼格式。在與H.264最高規格相同的視頻播放質量下,VP9有望為 網絡視頻服務節省一半的網絡帶寬。該視頻格式為基於瀏覽器的實時視頻會議工具WebRTC等應用提供一個低延遲、高質量的視頻編碼解決方案。作為業內第一 家VP8視頻編解碼IP提供商,芯原仍將是業內首家在Hantro視頻IP中提供VP9解碼支持的提供商。 7 x( p* g' n: G" l9 A+ f' v0 x3 L5 `1 a * G0 `8 S& H& ^7 e' d3 A/ O「無論是面向娛樂應用的消費類電子產品,還是面向安全與監控的基礎設施,高清視頻已經存在於我們生活的每個角落。基於Hantro G2多格式視頻解碼IP的優異性能,以及其對HEVC和VP9視頻格式的支持,客戶可以用高性價比的方案來應對高清視頻應用對網絡帶寬、傳輸速率、本地存 儲和功耗所帶來的挑戰。」芯原董事長兼總裁戴偉民博士表示,「我們相信HEVC和VP9視頻格式將最終取代H.264而遍佈各種電子設備之中。」 % Y, D; Z# Y* q9 l. |, s$ ]